FMC_OBR FMC_OBR 0x00 0x20 read-write 0x000000AA FFFF TZEN Trust zone enable bit 0: Disable Trust zone function 1: Enable Trust zone function 15 1 SRAM1_RST SRAM1 reset enable bit 0: no effect 1: clear SRAM1 data automatically, Effective after system reset 12 1 SPC Flash security protection value Flash security protection value 0xAA: No protection 0x55: security protection level 0.5 (available only when TZEN = 1) Others: Level 1 0 8 FMC_OBUSER FMC_OBUSER 0x04 0x20 read-write 0xFFFFFFFF FFFF USER Option byte USER value Option byte USER value 0 32 FMC_SECMCFG0 FMC_SECMCFG0 0x08 0x20 read-write 0x03FF0000 FFFF SECM0_EPAGE End page of secure mark area 0 If DMP0_ACCFG is 1, this bits cannot be modified. If SECM0_EPAGE < DMP0_EPAGE, SECERR bit will be set and discard this write. 16 10 SECM0_SPAGE Start page of secure mark area 0 If DMP0_ACCFG is 1, this bits cannot be modified 0 10 FMC_DMP0 FMC_DMP0 0x0C 0x20 read-write 0x00000000 FFFF DMP0EN DMP area 0 enable 0: disable. 1: enable. 31 1 DMP0_EPAGE End page of DMP area 0 End page of DMP area 0 16 10 FMC_OBWRP0 FMC_OBWRP0 0x10 0x20 read-write 0x000003FF FFFF WRP0_EPAGE End page of write protection area 0 End page of write protection area 0 16 10 WRP0_SPAGE Start page of write protection area 0 Start page of write protection area 0 0 10 FMC_SECMCFG1 FMC_SECMCFG1 0x14 0x20 read-write 0x000003FF FFFF SECM1_EPAGE End page of secure mark area 1 If DMP1_ACCFG is 1, this bits cannot be modified. If SECM1_EPAGE < DMP1_EPAGE, SECERR bit will be set and discard this write. 16 10 SECM1_SPAGE Start page of secure mark area 1 If DMP1_ACCFG is 1, this bits cannot be modified 0 10 FMC_DMP1 FMC_DMP1 0x18 0x20 read-write 0x00000000 FFFF DMP1EN DMP area 1 enable 0: disable 1: enable 31 1 DMP1_EPAGE End page of DMP area 1 End page of DMP area 1 16 10 FMC_OBWRP1 FMC_OBWRP1 0x1C 0x20 read-write 0x000003FF FFFF WRP1_EPAGE End page of write protection area 1 End page of write protection area 1 16 10 WRP1_SPAGE Start page of write protection area 1 Start page of write protection area 1 0 10 EFUSE_CTL EFUSE_CTL 0x00 0x20 read-write FFFF SWBOOT0 Efuse boot 0 bit enable 0: Select boot0_pad as BOOT0 output 1: Select efuse_boot0 as BOOT0 output 5 1 EFBOOT0 Efuse boot0 0: Efuse_boot0 = 0 1: Efuse_boot0 = 1 4 1 SWBOOT1 Efuse boot 1 bit enable 0: Select boot1_pad as BOOT1 output 1: Select efuse_boot1 as BOOT1 output 3 1 EFBOOT1 Efuse boot1 0: Efuse_boot1 = 0 1: Efuse_boot1 = 1 2 1 EFBOOTLK EFUSE_CTL register bit[5:2] lock bit 0: Unlock EFUSE_CTL register bit[5:2], these bits can be modify 1: Lock EFUSE_CTL register bit[5:2], these bits can not be modify 1 1 EFSB This bit needs to work with the bits[5:1] and GSSACDM in SYSCFG_GSSACMDR register to decide how to startup 0: Startup from Flash 1: Startup from Secure boot 0 1 EFUSE_TZCTL EFUSE_TZCTL 0x04 0x20 read-write FFFF VFCERT Verify firmware certificate 0: Disable firmware certificate verification 1: Enable firmware certificate verification 7 1 VFIMG Verify firmware image 0: Disable firmware image verification 1: Enable firmware image verification 6 1 DPLK EFUSE_DP register lock bit 0: Unlock EFUSE_DP register 1: Lock EFUSE_DP register 5 1 IGLK EFUSE_IAK_GSSA register lock bit 0: Unlock EFUSE_IAK_GSSA register 1: Lock EFUSE_IAK_GSSA register 4 1 RFLK EFUSE_RF_DATA register lock bit 0: Unlock EFUSE_RF_DATA register, and can be modified 1: Lock EFUSE_RF_DATA register, and can not be modified 3 1 ROTLK EFUSE_ROTPK_KEY register lock bit 0: Unlock EFUSE_ROTPK_KEY register 1: Lock EFUSE_ROTPK_KEY register 2 1 NDBG Debugging permission setting 0: Unlimited debugging 1: Can not debug 1 1 TZCTL_TZEN Trust zone enable bit 0: Disable trust zone function 1: Enable trust zone function 0 1 EFUSE_FP_CTL EFUSE_FP_CTL 0x08 0x20 read-write FFFF FP[7:0] Efuse flash protection value Bit[7:3]: Reserved Bit2: 0~32K write protection Bit1: Read protection level 0.5 Bit0: Read protection level 1 0 8 EFUSE_USER_CTL EFUSE_USER_CTL 0x0C 0x20 read-write FFFF UDLK EFUSE_USER_DATA register lock bit 0: Unlock EFUSE_USER_DATA register 1: Lock EFUSE_USER_DATA register 6 1 AESEN Lock EFUSE_AES_KEY register and enable AES decrypt function 0: Disable AES decrypt and AES key can be written 1: Enable AES decrypt and AES key can’t be written 5 1 MCUINITLK EFUSE_MCU_INIT_DATA register lock bit 0: MCU initialization parameters can be written when parameters have never been written 1: MCU initialization parameters can not be written 4 1 EFOPLK EFUSE_FP_CTL and EFUSE_USER_CTL register lock bit 0: Unlock EFUSE_RDP_CTL and EFUSE_USER_CTL register, these bytes can be modify when parameters have never been written 1: Lock EFUSE_RDP_CTL and EFUSE_USER_CTL register, these bytes can not be modify 3 1 NRSTDPSLP Reset option of entry deep sleep mode 0: Generate a reset instead of entering Deep-sleep mode 1: No reset when entering Deep-sleep mode 2 1 NRSTSTDBY Reset option of entry standby mode 0: Generate a reset instead of entering standby mode 1: No reset when entering standby mode 1 1 HWDG Free watchdog timer selection 0: Software free watchdog timer 1: Hardware free watchdog timer 0 1 EFUSE_MCU_INIT_DATA_0 EFUSE_MCU_INIT_DATA_0 0x10 0x20 read-write FFFF INITDATA_0[31:0] Efuse mcu_init value Efuse mcu_init value 0 32 EFUSE_MCU_INIT_DATA_1 EFUSE_MCU_INIT_DATA_1 0x14 0x20 read-write FFFF INITDATA_1[31:0] Efuse mcu_init value Efuse mcu_init value 0 32 EFUSE_MCU_INIT_DATA_2 EFUSE_MCU_INIT_DATA_2 0x18 0x20 read-write FFFF INITDATA_2[31:0] Efuse mcu_init value Efuse mcu_init value 0 32 EFUSE_AES_KEY_0 EFUSE_AES_KEY_0 0x1C 0x20 read-write FFFF AESKEY_0[31:0] Efuse AES key value Efuse AES key value 0 32 EFUSE_AES_KEY_1 EFUSE_AES_KEY_1 0x20 0x20 read-write FFFF AESKEY_1[31:0] Efuse AES key value Efuse AES key value 0 32 EFUSE_AES_KEY_2 EFUSE_AES_KEY_2 0x24 0x20 read-write FFFF AESKEY_2[31:0] Efuse AES key value Efuse AES key value 0 32 EFUSE_AES_KEY_3 EFUSE_AES_KEY_3 0x28 0x20 read-write FFFF AESKEY_3[31:0] Efuse AES key value Efuse AES key value 0 32 EFUSE_RoTPK_0 EFUSE_RoTPK_0 0x2C 0x20 read-write FFFF RKEY_0[31:0] EFUSE RoTPK or its hash value EFUSE RoTPK or its hash value 0 32 EFUSE_RoTPK_1 EFUSE_RoTPK_1 0x30 0x20 read-write FFFF RKEY_1[31:0] EFUSE RoTPK or its hash value EFUSE RoTPK or its hash value 0 32 EFUSE_RoTPK_2 EFUSE_RoTPK_2 0x34 0x20 read-write FFFF RKEY_2[31:0] EFUSE RoTPK or its hash value EFUSE RoTPK or its hash value 0 32 EFUSE_RoTPK_3 EFUSE_RoTPK_3 0x38 0x20 read-write FFFF RKEY_3[31:0] EFUSE RoTPK or its hash value EFUSE RoTPK or its hash value 0 32 EFUSE_RoTPK_4 EFUSE_RoTPK_4 0x3C 0x20 read-write FFFF RKEY_4[31:0] EFUSE RoTPK or its hash value EFUSE RoTPK or its hash value 0 32 EFUSE_RoTPK_5 EFUSE_RoTPK_5 0x40 0x20 read-write FFFF RKEY_5[31:0] EFUSE RoTPK or its hash value EFUSE RoTPK or its hash value 0 32 EFUSE_RoTPK_6 EFUSE_RoTPK_6 0x44 0x20 read-write FFFF RKEY_6[31:0] EFUSE RoTPK or its hash value EFUSE RoTPK or its hash value 0 32 EFUSE_RoTPK_7 EFUSE_RoTPK_7 0x48 0x20 read-write FFFF RKEY_7[31:0] EFUSE RoTPK or its hash value EFUSE RoTPK or its hash value 0 32 EFUSE_DP_0 EFUSE_DP_0 0x4C 0x20 read-write FFFF DP_0[31:0] Efuse Debug password value Efuse Debug password value 0 32 EFUSE_DP_1 EFUSE_DP_1 0x50 0x20 read-write FFFF DP_1[31:0] Efuse Debug password value Efuse Debug password value 0 32 EFUSE_IAK_GSSA_0 EFUSE_IAK_GSSA_0 0x54 0x20 read-write FFFF IAKRSS_0[31:0] Efuse IAK/GSSA value The properties of this register depend on the IAKSEL bit in the EFUSE_CS register 0 32 EFUSE_IAK_GSSA_1 EFUSE_IAK_GSSA_1 0x58 0x20 read-write FFFF IAKRSS_1[31:0] Efuse IAK/GSSA value The properties of this register depend on the IAKSEL bit in the EFUSE_CS register 0 32 EFUSE_IAK_GSSA_2 EFUSE_IAK_GSSA_2 0x5C 0x20 read-write FFFF IAKRSS_2[31:0] Efuse IAK/GSSA value The properties of this register depend on the IAKSEL bit in the EFUSE_CS register 0 32 EFUSE_IAK_GSSA_3 EFUSE_IAK_GSSA_3 0x60 0x20 read-write FFFF IAKRSS_3[31:0] Efuse IAK/GSSA value The properties of this register depend on the IAKSEL bit in the EFUSE_CS register 0 32 EFUSE_IAK_GSSA_4 EFUSE_IAK_GSSA_4 0x64 0x20 read-write FFFF IAKRSS_4[31:0] Efuse IAK/GSSA value The properties of this register depend on the IAKSEL bit in the EFUSE_CS register 0 32 EFUSE_IAK_GSSA_5 EFUSE_IAK_GSSA_5 0x68 0x20 read-write FFFF IAKRSS_5[31:0] Efuse IAK/GSSA value The properties of this register depend on the IAKSEL bit in the EFUSE_CS register 0 32 EFUSE_IAK_GSSA_6 EFUSE_IAK_GSSA_6 0x6C 0x20 read-write FFFF IAKRSS_6[31:0] Efuse IAK/GSSA value The properties of this register depend on the IAKSEL bit in the EFUSE_CS register 0 32 EFUSE_IAK_GSSA_7 EFUSE_IAK_GSSA_7 0x70 0x20 read-write FFFF IAKRSS_7[31:0] Efuse IAK/GSSA value The properties of this register depend on the IAKSEL bit in the EFUSE_CS register 0 32 EFUSE_IAK_GSSA_8 EFUSE_IAK_GSSA_8 0x74 0x20 read-write FFFF IAKRSS_8[31:0] Efuse IAK/GSSA value The properties of this register depend on the IAKSEL bit in the EFUSE_CS register 0 32 EFUSE_IAK_GSSA_9 EFUSE_IAK_GSSA_9 0x78 0x20 read-write FFFF IAKRSS_9[31:0] Efuse IAK/GSSA value The properties of this register depend on the IAKSEL bit in the EFUSE_CS register 0 32 EFUSE_IAK_GSSA_10 EFUSE_IAK_GSSA_10 0x7C 0x20 read-write FFFF IAKRSS_10[31:0] Efuse IAK/GSSA value The properties of this register depend on the IAKSEL bit in the EFUSE_CS register 0 32 EFUSE_IAK_GSSA_11 EFUSE_IAK_GSSA_11 0x80 0x20 read-write FFFF IAKRSS_11[31:0] Efuse IAK/GSSA value The properties of this register depend on the IAKSEL bit in the EFUSE_CS register 0 32 EFUSE_IAK_GSSA_12 EFUSE_IAK_GSSA_12 0x84 0x20 read-write FFFF IAKRSS_12[31:0] Efuse IAK/GSSA value The properties of this register depend on the IAKSEL bit in the EFUSE_CS register 0 32 EFUSE_IAK_GSSA_13 EFUSE_IAK_GSSA_13 0x88 0x20 read-write FFFF IAKRSS_13[31:0] Efuse IAK/GSSA value The properties of this register depend on the IAKSEL bit in the EFUSE_CS register 0 32 EFUSE_IAK_GSSA_14 EFUSE_IAK_GSSA_14 0x8C 0x20 read-write FFFF IAKRSS_14[31:0] Efuse IAK/GSSA value The properties of this register depend on the IAKSEL bit in the EFUSE_CS register 0 32 EFUSE_IAK_GSSA_15 EFUSE_IAK_GSSA_15 0x90 0x20 read-write FFFF IAKRSS_15[31:0] Efuse IAK/GSSA value The properties of this register depend on the IAKSEL bit in the EFUSE_CS register 0 32 EFUSE_PUID_0 EFUSE_PUID_0 0x94 0x20 read-write FFFF UID_0[31:0] Efuse MCU UID value Efuse MCU UID value 0 32 EFUSE_PUID_1 EFUSE_PUID_1 0x98 0x20 read-write FFFF UID_1[31:0] Efuse MCU UID value Efuse MCU UID value 0 32 EFUSE_PUID_2 EFUSE_PUID_2 0x9C 0x20 read-write FFFF UID_2[31:0] Efuse MCU UID value Efuse MCU UID value 0 32 EFUSE_PUID_3 EFUSE_PUID_3 0xA0 0x20 read-write FFFF UID_3[31:0] Efuse MCU UID value Efuse MCU UID value 0 32 EFUSE_HUK_KEY_0 EFUSE_HUK_KEY_0 0xA4 0x20 read-write FFFF HKEY_0[31:0] Efuse HUK value Efuse HUK value 0 32 EFUSE_HUK_KEY_1 EFUSE_HUK_KEY_1 0xA8 0x20 read-write FFFF HKEY_1[31:0] Efuse HUK value Efuse HUK value 0 32 EFUSE_HUK_KEY_2 EFUSE_HUK_KEY_2 0xAC 0x20 read-write FFFF HKEY_2[31:0] Efuse HUK value Efuse HUK value 0 32 EFUSE_HUK_KEY_3 EFUSE_HUK_KEY_3 0xB0 0x20 read-write FFFF HKEY_3[31:0] Efuse HUK value Efuse HUK value 0 32 EFUSE_RF_DATA_0 EFUSE_RF_DATA_0 0xB4 0x20 read-write FFFF RFDATA_0[31:0] Efuse RF data value Efuse RF data value 0 32 EFUSE_RF_DATA_1 EFUSE_RF_DATA_1 0xB8 0x20 read-write FFFF RFDATA_1[31:0] Efuse RF data value Efuse RF data value 0 32 EFUSE_RF_DATA_2 EFUSE_RF_DATA_2 0xBC 0x20 read-write FFFF RFDATA_2[31:0] Efuse RF data value Efuse RF data value 0 32 EFUSE_RF_DATA_3 EFUSE_RF_DATA_3 0xC0 0x20 read-write FFFF RFDATA_3[31:0] Efuse RF data value Efuse RF data value 0 32 EFUSE_RF_DATA_4 EFUSE_RF_DATA_4 0xC4 0x20 read-write FFFF RFDATA_4[31:0] Efuse RF data value Efuse RF data value 0 32 EFUSE_RF_DATA_5 EFUSE_RF_DATA_5 0xC8 0x20 read-write FFFF RFDATA_5[31:0] Efuse RF data value Efuse RF data value 0 32 EFUSE_RF_DATA_6 EFUSE_RF_DATA_6 0xCC 0x20 read-write FFFF RFDATA_6[31:0] Efuse RF data value Efuse RF data value 0 32 EFUSE_RF_DATA_7 EFUSE_RF_DATA_7 0xD0 0x20 read-write FFFF RFDATA_7[31:0] Efuse RF data value Efuse RF data value 0 32 EFUSE_RF_DATA_8 EFUSE_RF_DATA_8 0xD4 0x20 read-write FFFF RFDATA_8[31:0] Efuse RF data value Efuse RF data value 0 32 EFUSE_RF_DATA_9 EFUSE_RF_DATA_9 0xD8 0x20 read-write FFFF RFDATA_9[31:0] Efuse RF data value Efuse RF data value 0 32 EFUSE_RF_DATA_10 EFUSE_RF_DATA_10 0xDC 0x20 read-write FFFF RFDATA_10[31:0] Efuse RF data value Efuse RF data value 0 32 EFUSE_RF_DATA_11 EFUSE_RF_DATA_11 0xE0 0x20 read-write FFFF RFDATA_11[31:0] Efuse RF data value Efuse RF data value 0 32 EFUSE_USER_data_0 EFUSE_USER_data_0 0xE4 0x20 read-write FFFF USERDATA_0[31:0] Efuse USER_DATA value Efuse USER_DATA value 0 32 EFUSE_USER_data_1 EFUSE_USER_data_1 0xE8 0x20 read-write FFFF USERDATA_1[31:0] Efuse USER_DATA value Efuse USER_DATA value 0 32 EFUSE_USER_data_2 EFUSE_USER_data_2 0xEC 0x20 read-write FFFF USERDATA_2[31:0] Efuse USER_DATA value Efuse USER_DATA value 0 32 EFUSE_USER_data_3 EFUSE_USER_data_3 0xF0 0x20 read-write FFFF USERDATA_3[31:0] Efuse USER_DATA value Efuse USER_DATA value 0 32 EFUSE_USER_data_4 EFUSE_USER_data_4 0xF4 0x20 read-write FFFF USERDATA_4[31:0] Efuse USER_DATA value Efuse USER_DATA value 0 32 EFUSE_USER_data_5 EFUSE_USER_data_5 0xF8 0x20 read-write FFFF USERDATA_5[31:0] Efuse USER_DATA value Efuse USER_DATA value 0 32 EFUSE_USER_data_6 EFUSE_USER_data_6 0xFC 0x20 read-write FFFF USERDATA_6[31:0] Efuse USER_DATA value Efuse USER_DATA value 0 32 EFUSE_USER_data_7 EFUSE_USER_data_7 0x100 0x20 read-write FFFF USERDATA_7[31:0] Efuse USER_DATA value Efuse USER_DATA value 0 32