FMC_OBR FMC_OBR 0x00 0x20 read-write 0x00000EAA FFFF SRAM1_RST SRAM1 reset enable bit. 0: No effect 1: Clear SRAM1 data automatically. Effective after system reset 12 1 NRST_STOP Vcore domain Stop entry reset option status bit. 0: A reset is generated when entering Stop mode on Vcore domain 1: No reset generated when entering Stop mode on Vcore domain 11 1 NRST_STDBY Vcore domain Standby entry reset option status bit. 0: A reset is generated when entering Standby mode on Vcore domain 1: No reset generated when entering Standby mode on Vcore domain 10 1 NWDG_HW IWDG option byte. 0: IWDG is hardware watchdog 1: IWDG is software watchdog 9 1 SPC[7:0] Option byte security protection value. Effective after system reset. 0xAA: No protection Any value except 0xAA: Protection level low 0 8 FMC_OBUSER FMC_OBUSER 0x04 0x20 read-write 0xFFFFFFFF FFFF USER[31:0] Option byte USER value. USER is subject to this bit field configuration 0 32 FMC_OBWRP0 FMC_OBWRP0 0x08 0x20 read-write 0x000003FF FFFF WRP0_EPAGE[9:0] End page of write protection area 0. End page of write protection area 0 16 10 WRP0_SPAGE[9:0] Start page of write protection area 0. Start page of write protection area 0 0 10 FMC_OBWRP1 FMC_OBWRP1 0x0C 0x20 read-write 0x000003FF FFFF WRP1_EPAGE[9:0] End page of write protection area 1. End page of write protection area 1 16 10 WRP1_SPAGE[9:0] Start page of write protection area 1. Start page of write protection area 1 0 10 EFUSE_CTL0 EFUSE_CTL0 0x00 0x20 read-write FFFF SWBOOT0 Efuse BOOT0 bit enable. 0: Select boot0_pad as BOOT0 output 1: Select Efuse_boot0 as BOOT0 output 5 1 EFBOOT0 Efuse BOOT0. 0: Efuse_boot0 = 0 1: Efuse_boot0 = 1 4 1 SWBOOT1 Efuse BOOT1 bit enable. 0: Select boot1_pad as BOOT1 output 1: Select Efuse_boot1 as BOOT1 output 3 1 EFBOOT1 Efuse BOOT1. 0: Efuse_boot1 = 0 1: Efuse_boot1 = 1 2 1 EFBOOTLK EFUSE_CTL0 register bits[5:2] lock bit. 0: Unlock EFUSE_CTL register bits[5:2], these bits can be modify 1: Lock EFUSE_CTL register bits[5:2],these bits can not be modify 1 1 EFSB SRAM1 reset enable bit. This bit needs to work with the bits[5:1] to decide how to startup 0: Startup from Flash 1: Startup from secure boot 0 1 EFUSE_CTL1 EFUSE_CTL1 0x04 0x20 read-write FFFF VFCERT Verify firmware certificate. 0: Disable firmware certificate verification 1: Enable firmware certificate verification 7 1 VFIMG Verify firmware image. 0: Disable firmware image verification 1: Enable firmware image verification 6 1 OBLK Option bytes lock bit. 0: Unlock option bytes 1: Lock option bytes 3 1 ROTLK EFUSE_ROTPK_KEY register lock bit. 0: Unlock EFUSE_ROTPK_KEY register, these bytes can be modified 1: Lock EFUSE_ROTPK_KEY register, these bytes can not be modified 2 1 NDBG Debugging permission setting. 0: Unlimited debugging 1: Can not debug 1 1 EFUSE_FPCTL EFUSE_FPCTL 0x08 0x20 read-write FFFF FP[2] Efuse flash protection value. 0~32K write protection 2 1 FP[0] Efuse flash protection value. Read protection level 1 0 1 EFUSE_USERCTL EFUSE_USERCTL 0x0C 0x20 read-write FFFF UDLK EFUSE_USER_DATA register lock bit. 0: Unlock EFUSE_USER_DATA register, and register can be modified 1: Lock EFUSE_USER_DATA register, and register can not be modified 6 1 AESEN Lock EFUSE_AES_KEY register and enable AES decrypt function. 0: Disable AES decrypt and unlock EFUSE_AES_KEY register and AES key can be modified 1: Enable AES decrypt and lock EFUSE_AES_KEY register and AES key can not be modified 5 1 EFOPLK EFUSE_FPCTL and EFUSE_USERCTL register lock bit. 0: Unlock EFUSE_FPCTL and EFUSE_USERCTL register, these bytes can be modified 1: Lock EFUSE_FPCTL and EFUSE_USERCTL register, these bytes can not be modified 3 1 LOGUART Secure Boot Log UART selection. 0: UART2 (PA6/PA7) 1: UART1 (PA4/PA5) 1 1 SBCLK Secure boot clock source selection. 0: IRC16M 1: External HXTAL 0 1 EFUSE_RES0 EFUSE_RES0 0x10 0x20 read-write FFFF RES0[31:0] Efuse reserved bytes. Efuse reserved bytes 0 32 EFUSE_RES1 EFUSE_RES1 0x14 0x20 read-write FFFF RES1[31:0] Efuse reserved bytes. Efuse reserved bytes 0 32 EFUSE_RES2 EFUSE_RES2 0x18 0x20 read-write FFFF RES2[31:0] Efuse reserved bytes. Efuse reserved bytes 0 32 EFUSE_AESKEY0 EFUSE_AESKEY0 0x1C 0x20 read-write FFFF AESKEY0[31:0] Efuse AES key value. Efuse AES key value 0 32 EFUSE_AESKEY1 EFUSE_AESKEY1 0x20 0x20 read-write FFFF AESKEY1[31:0] Efuse AES key value. Efuse AES key value 0 32 EFUSE_AESKEY2 EFUSE_AESKEY2 0x24 0x20 read-write FFFF AESKEY2[31:0] Efuse AES key value. Efuse AES key value 0 32 EFUSE_AESKEY3 EFUSE_AESKEY3 0x28 0x20 read-write FFFF AESKEY3[31:0] Efuse AES key value. Efuse AES key value 0 32 EFUSE_ROTPKKEY0 EFUSE_ROTPKKEY0 0x2C 0x20 read-write FFFF RKEY0[31:0] Efuse RoTPK or its HASH value. Efuse RoTPK or its HASH value 0 32 EFUSE_ROTPKKEY1 EFUSE_ROTPKKEY1 0x30 0x20 read-write FFFF RKEY1[31:0] Efuse RoTPK or its HASH value. Efuse RoTPK or its HASH value 0 32 EFUSE_ROTPKKEY2 EFUSE_ROTPKKEY2 0x34 0x20 read-write FFFF RKEY2[31:0] Efuse RoTPK or its HASH value. Efuse RoTPK or its HASH value 0 32 EFUSE_ROTPKKEY3 EFUSE_ROTPKKEY3 0x38 0x20 read-write FFFF RKEY3[31:0] Efuse RoTPK or its HASH value. Efuse RoTPK or its HASH value 0 32 EFUSE_ROTPKKEY4 EFUSE_ROTPKKEY4 0x3C 0x20 read-write FFFF RKEY4[31:0] Efuse RoTPK or its HASH value. Efuse RoTPK or its HASH value 0 32 EFUSE_ROTPKKEY5 EFUSE_ROTPKKEY5 0x40 0x20 read-write FFFF RKEY5[31:0] Efuse RoTPK or its HASH value. Efuse RoTPK or its HASH value 0 32 EFUSE_ROTPKKEY6 EFUSE_ROTPKKEY6 0x44 0x20 read-write FFFF RKEY6[31:0] Efuse RoTPK or its HASH value. Efuse RoTPK or its HASH value 0 32 EFUSE_ROTPKKEY7 EFUSE_ROTPKKEY7 0x48 0x20 read-write FFFF RKEY7[31:0] Efuse RoTPK or its HASH value. Efuse RoTPK or its HASH value 0 32 EFUSE_PUID0 EFUSE_PUID0 0x4C 0x20 read FFFF UID0[31:0] Efuse MCU UID value. Efuse MCU UID value 0 32 EFUSE_PUID1 EFUSE_PUID1 0x50 0x20 read FFFF UID1[31:0] Efuse MCU UID value. Efuse MCU UID value 0 32 EFUSE_PUID2 EFUSE_PUID2 0x54 0x20 read FFFF UID2[31:0] Efuse MCU UID value. Efuse MCU UID value 0 32 EFUSE_PUID3 EFUSE_PUID3 0x58 0x20 read FFFF UID3[31:0] Efuse MCU UID value. Efuse MCU UID value 0 32 EFUSE_HUKKEY0 EFUSE_HUKKEY0 0x5C 0x20 read FFFF HKEY0[31:0] Efuse HUK key value. Efuse HUK key value 0 32 EFUSE_HUKKEY1 EFUSE_HUKKEY1 0x60 0x20 read FFFF HKEY1[31:0] Efuse HUK key value. Efuse HUK key value 0 32 EFUSE_HUKKEY2 EFUSE_HUKKEY2 0x64 0x20 read FFFF HKEY2[31:0] Efuse HUK key value. Efuse HUK key value 0 32 EFUSE_HUKKEY3 EFUSE_HUKKEY3 0x68 0x20 read FFFF HKEY3[31:0] Efuse HUK key value. Efuse HUK key value 0 32 EFUSE_USER_DATA0 EFUSE_USER_DATA0 0x6C 0x20 read-write FFFF USERDATA0[31:0] Efuse USER_DATA value. Efuse USER_DATA value 0 32 EFUSE_USER_DATA1 EFUSE_USER_DATA1 0x70 0x20 read-write FFFF USERDATA1[31:0] Efuse USER_DATA value. Efuse USER_DATA value 0 32 EFUSE_USER_DATA2 EFUSE_USER_DATA2 0x74 0x20 read-write FFFF USERDATA2[31:0] Efuse USER_DATA value. Efuse USER_DATA value 0 32 EFUSE_USER_DATA3 EFUSE_USER_DATA3 0x78 0x20 read-write FFFF USERDATA3[31:0] Efuse USER_DATA value. Efuse USER_DATA value 0 32 EFUSE_USER_DATA4 EFUSE_USER_DATA4 0x7C 0x20 read-write FFFF USERDATA4[31:0] Efuse USER_DATA value. Efuse USER_DATA value 0 32 EFUSE_USER_DATA5 EFUSE_USER_DATA5 0x80 0x20 read-write FFFF USERDATA5[31:0] Efuse USER_DATA value. Efuse USER_DATA value 0 32 EFUSE_USER_DATA6 EFUSE_USER_DATA6 0x84 0x20 read-write FFFF USERDATA6[31:0] Efuse USER_DATA value. Efuse USER_DATA value 0 32 EFUSE_USER_DATA7 EFUSE_USER_DATA7 0x88 0x20 read-write FFFF USERDATA7[31:0] Efuse USER_DATA value. Efuse USER_DATA value 0 32