SPC SPC 0x0 0x8 read-write 0xA5 FFFF SPC Option bytes security protection value Option bytes security protection value 0xA5 : No security protection Any value except 0xA5 or 0xCC : Protection level low 0xCC : Protection level high 0 8 SPC_N SPC_N 0x1 0x8 read 0x5A 0 SPC_N SPC complement value SPC complement value 0 8 USER USER 0x2 0x8 read-write FFFF FFFF VDSEL[1:0] VDSEL[1:0] (LVD0 voltage level select) VDSEL[1:0] 00: 3.84 V is selected 01: 2.82 V is selected 10: 2.51 V is selected Settings other than above are prohibited when the voltage detection 0 circuit is used. 6 2 FWDGSPD_STDBY FWDGSPD_STDBY FWDGSPD_STDBY 0: Suspend the free watchdog in standby mode 1: Run the free watchdog in standby mode 5 1 FWDGSPD_DPSLP FWDGSPD_DPSLP FWDGSPD_DPSLP 0: Suspend the free watchdog in deepsleep mode 1: Run the free watchdog in deepsleep mode 4 1 LVDAS LVDAS LVDAS 0: Voltage monitoring 0 reset is enabled after a reset 1: Voltage monitoring 0 reset is disabled after a reset 3 1 nRST_STDBY nRST_STDBY nRST_STDBY 0: Generate a reset instead of entering standby mode 1: No reset when entering standby mode 2 1 nRST_DPSLP nRST_DPSLP nRST_DPSLP 0: Generate a reset instead of entering deep-sleep mode 1: No reset when entering deep-sleep mode 1 1 nFWDG_HW nFWDG_HW nFWDG_HW 0: Hardware free watchdog 1: Software free watchdog 0 1 USER_N USER_N 0x3 0x8 read FFFF 0 USER_N USER complement value USER complement value 0 8 DATA[7:0] DATA[7:0] 0x4 0x8 read-write FFFF FFFF DATA[7:0] User defined data bit 7 to 0 User defined data bit 7 to 0 0 8 DATA_N[7:0] DATA_N[7:0] 0x5 0x8 read FFFF 0 DATA_N[7:0] DATA complement value bit 7 to 0 DATA complement value bit 7 to 0 0 8 DATA[15:8] DATA[15:8] 0x6 0x8 read-write FFFF FFFF DATA[15:8] User defined data bit 15 to 8 User defined data bit 15 to 8 0 8 DATA_N[15:8] DATA_N[15:8] 0x7 0x8 read FFFF 0 DATA_N[15:8] DATA complement value bit 15 to 8 DATA complement value bit 15 to 8 0 8 WP[7:0] WP[7:0] 0x8 0x8 read-write FFFF FFFF WP[7] 0x800E000~0x800FFFF Page erase / program protection bit 7(0x800E000~0x800FFFF) 0: Protection active 1: Unprotected 7 1 WP[6] 0x800C000~0x800DFFF Page erase / program protection bit 6(0x800C000~0x800DFFF) 0: Protection active 1: Unprotected 6 1 WP[5] 0x800A000~0x800BFFF Page erase / program protection bit 5(0x800A000~0x800BFFF) 0: Protection active 1: Unprotected 5 1 WP[4] 0x8008000~0x8009FFF Page erase / program protection bit 4(0x8008000~0x8009FFF) 0: Protection active 1: Unprotected 4 1 WP[3] 0x8006000~0x8007FFF Page erase / program protection bit 3(0x8006000~0x8007FFF) 0: Protection active 1: Unprotected 3 1 WP[2] 0x8004000~0x8005FFF Page erase / program protection bit 2(0x8004000~0x8005FFF) 0: Protection active 1: Unprotected 2 1 WP[1] 0x8002000~0x8003FFF Page erase / program protection bit 1(0x8002000~0x8003FFF) 0: Protection active 1: Unprotected 1 1 WP[0] 0x8000000~0x8001FFF Page erase / program protection bit 0(0x8000000~0x8001FFF) 0: Protection active 1: Unprotected 0 1 WP_N[7:0] WP_N[7:0] 0x9 0x8 read FFFF 0 WP_N[7:0] WP complement value bit 7 to 0 WP complement value bit 7 to 0 0 8 WP[15:8] WP[15:8] 0xA 0x8 read-write FFFF FFFF WP[15] 0x801E000~0x801FFFF Page erase / program protection bit 15(0x801E000~0x801FFFF) 7 1 WP[14] 0x801C000~0x801DFFF Page erase / program protection bit 14(0x801C000~0x801DFFF) 6 1 WP[13] 0x801A000~0x801BFFF Page erase / program protection bit 13(0x801A000~0x801BFFF) 5 1 WP[12] 0x8018000~0x8019FFF Page erase / program protection bit 12(0x8018000~0x8019FFF) 4 1 WP[11] 0x8016000~0x8017FFF Page erase / program protection bit 11(0x8016000~0x8017FFF) 3 1 WP[10] 0x8014000~0x8015FFF Page erase / program protection bit 10(0x8014000~0x8015FFF) 2 1 WP[9] 0x8012000~0x8013FFF Page erase / program protection bit 9(0x8012000~0x8013FFF) 1 1 WP[8] 0x8010000~0x8011FFF Page erase / program protection bit 8(0x8010000~0x8011FFF) 0 1 WP_N[15:8] WP_N[15:8] 0xB 0x8 read FFFF 0 WP_N[15:8] WP complement value bit 15 to 8 WP complement value bit 15 to 8 0 8 WP[23:16] WP[23:16] 0xC 0x8 read-write FFFF FFFF WP[23] 0x802E000~0x803FFFF Page erase / program protection bit 23(0x802C000~0x803FFFF) 7 1 WP[22] 0x802C000~0x802DFFF Page erase / program protection bit 22(0x802C000~0x802DFFF) 6 1 WP[21] 0x802A000~0x802BFFF Page erase / program protection bit 21(0x802A000~0x802BFFF) 5 1 WP[20] 0x8028000~0x8029FFF Page erase / program protection bit 20(0x8028000~0x8029FFF) 4 1 WP[19] 0x8026000~0x8027FFF Page erase / program protection bit 19(0x8026000~0x8027FFF) 3 1 WP[18] 0x8024000~0x8025FFF Page erase / program protection bit 18(0x8024000~0x8025FFF) 2 1 WP[17] 0x8022000~0x8023FFF Page erase / program protection bit 17(0x8022000~0x8023FFF) 1 1 WP[16] 0x8020000~0x8021FFF Page erase / program protection bit 16(0x8020000~0x8021FFF) 0 1 WP_N[23:16] WP_N[23:16] 0xD 0x8 read FFFF 0 WP_N[23:16] WP complement value bit 23 to 16 WP complement value bit 23 to 16 0 8 WP[31:24] WP[31:24] 0xE 0x8 read-write FFFF FFFF WP[31] 0x880E000~0x880FFFF Page erase / program protection bit 31(0x880E000~0x880FFFF) 7 1 WP[30] 0x880C000~0x880DFFF Page erase / program protection bit 30(0x880C000~0x880DFFF) 6 1 WP[29] 0x880A000~0x880BFFF Page erase / program protection bit 29(0x880A000~0x880BFFF) 5 1 WP[28] 0x8808000~0x8809FFF Page erase / program protection bit 28(0x8808000~0x8809FFF) 4 1 WP[27] 0x8806000~0x8807FFF Page erase / program protection bit 27(0x8806000~0x8807FFF) 3 1 WP[26] 0x8804000~0x8805FFF Page erase / program protection bit 26(0x8804000~0x8805FFF) 2 1 WP[25] 0x8802000~0x8803FFF Page erase / program protection bit 25(0x8802000~0x8803FFF) 1 1 WP[24] 0x8800000~0x8801FFF Page erase / program protection bit 24(0x8800000~0x8801FFF) 0 1 WP_N[31:24] WP_N[31:24] 0xF 0x8 read FFFF 0 WP_N[31:24] WP complement value bit 31 to 24 WP complement value bit 31 to 24 0 8 USER_1 USER_1 0x10 0x8 read-write FFFF FFFF nRST_MODE nRST_MODE nRST_MODE 00: Reserved 01: Reset input only 10: GPIO PN5 mode 11: Reset input / output 6 2 SWDMOD SWDMOD SWDMOD 0: SWD off 1: SWD normal work mode 2 1 SRAMECCEN SRAMECCEN SRAMECCEN 0: Disable SRAM ECC 1: Enable SRAM ECC 1 1 nWWDG_HW nWWDG_HW nWWDG_HW 0: Hardware window watchdog 1: Software window watchdog 0 1 USER_1_N USER_1_N 0x11 0x8 read FFFF 0 USER_1_N USER_1 complement value USER_1 complement value 0 8 WWDGT_0 WWDGT_0 0x12 0x8 read-write FFFF FFFF WWDGT_WDGTEN WWDGT_WDGTEN WWDGT_WDGTEN: 0: Disable WWDG to generate a reset 1: Enable WWDG to generate a reset 7 1 WWDGT_EWIE WWDGT_EWIE WWDGT_EWIE 0: Disable early wakeup interrupt 1: Enable early wakeup interrupt 6 1 WWDGT_WEPS WWDGT window end position WWDGT_WEPS: WWDGT window end position 00: 75% 01: 50% 10: 25% 11: 0% (No window end position setting) 4 2 WWDGT_WSPS WWDGT window start position WWDGT_WSPS: WWDGT window start position 00: 25% 01: 50% 10: 75% 11: 100% (No window start position setting) 2 2 WWDGT_PSC WWDGT prescaler WWDGT_PSC: WWDGT prescaler 0 2 WWDGT_0_N WWDGT_0_N 0x13 0x8 read FFFF 0 WWDGT_0_N WWDGT_0 complement value WWDGT_0 complement value 0 8 WWDGT_1 WWDGT_1 0x14 0x8 read-write FFFF FFFF WWDG_CNT [13:6] The value of the watchdog timer counter bit 13 to 6 in Hardware start mode WWDG_CNT [13:6] The value of the watchdog timer counter bit 13 to 6 in Hardware start mode 0 8 WWDGT_1_N WWDGT_1_N 0x15 0x8 read FFFF 0 WWDGT_1_N WWDGT_1 complement value WWDGT_1 complement value 0 8 WWDGT_2 WWDGT_2 0x16 0x8 read-write FFFF FFFF WWDG_CNT [5:0] The value of the watchdog timer counter bit 5 to 0 in Hardware start mode WWDG_CNT [5:0] The value of the watchdog timer counter bit 5 to 0 in Hardware start mode 0 6 WWDGT_2_N WWDGT_2_N 0x17 0x8 read FFFF 0 WWDGT_2_N WWDGT_2 complement value WWDGT_2 complement value 0 8 FWDGT_0 FWDGT_0 0x18 0x8 read-write FFFF FFFF FWDGT_RLD [7:0] The value of the free watchdog timer counter reload value bit 7 to 0 in hardware start mode. FWDGT_WDGTEN: The value of the free watchdog timer counter reload value bit 7 to 0 in hardware start mode. 0 8 FWDGT_0_N FWDGT_0_N 0x19 0x8 read FFFF 0 FWDGT_0_N FWDGT_0 complement value FWDGT_0 complement value 0 8 FWDGT_1 FWDGT_1 0x1A 0x8 read-write FFFF FFFF FWDGT_WDGTEN FWDGT_WDGTEN FWDGT_WDGTEN: 0: Disable FWDG to generate a reset 1: Enable FWDG to generate a reset 7 1 FWDGT_PSC [2:0] Free watchdog timer prescaler selection. FWDGT_PSC [2:0] Free watchdog timer prescaler selection. 4 3 FWDGT_WND [3:0] FWDGT_WND [3:0] FWDGT_WND [3:0] The value of the free watchdog counter window value bit 3 to 0 in hardware start mode. 0 4 FWDGT_1_N FWDGT_1_N 0x1B 0x8 read FFFF 0 FWDGT_1_N FWDGT_1 complement value FWDGT_1 complement value 0 8 FWDGT_2 FWDGT_2 0x1C 0x8 read-write FFFF FFFF FWDGT_WND [11:4] FWDGT_WND [11:4] FWDGT_WND [11:4] The value of the free watchdog counter window value bit 11 to 4 in hardware start mode. 0 8 FWDGT_2_N FWDGT_2_N 0x1D 0x8 read FFFF 0 FWDGT_2_N FWDGT_2 complement value FWDGT_2 complement value 0 8 FWDGT_3 FWDGT_3 0x1E 0x8 read-write FFFF FFFF FWDGT_RLD [11:8] FWDGT_RLD [11:8] FWDGT_RLD [11:8] The value of the free watchdog timer counter reload value bit 11 to 8 in hardware start mode. 0 4 FWDGT_3_N FWDGT_3_N 0x1F 0x8 read FFFF 0 FWDGT_3_N FWDGT_3 complement value FWDGT_3 complement value 0 8 OTP OTP 0x20 0x40 128 0x0 0x01 0x1FFF7000 0x1FFF71FF OTP_Block OTP_Block 0x1FFF7000 0x1FFF71FF 0x0 0x200 0x00 0 0