FMC_OBSTAT0_EFT FMC_OBSTAT0_EFT 0x00 0x20 read 0x01C6AAD0 FFFF IOSPDOPEN Allowed enable status bit for I/O speed optimization at low-voltage Allowed enable status bit for I/O speed optimization at low-voltage. 0: Chip operating voltage greater than 2.5V, so I/O speed optimization is not allowed 1: Chip operating voltage is less than 2.5V, so I/O speed optimization is allowed 29 1 DTCM1ECCEN DTCM1 ECC function enable status bit DTCM1 ECC function enable status bit 0: Disable CPU DTCM1 ECC function 1: Enable CPU DTCM1 ECC function 24 1 DTCM0ECCEN DTCM0 ECC function enable status bit DTCM0 ECC function enable status bit 0: Disable CPU DTCM0 ECC function 1: Enable CPU DTCM0 ECC function 23 1 ITCMECCEN ITCM ECC function enable status bit ITCM ECC function enable status bit 0: Disable CPU ITCM ECC function 1: Enable CPU ITCM ECC function 22 1 SCR Secure mode status bit Secure mode status bit 0: Disable secure mode. 1: Enable secure mode. 21 1 FWDGSPD_STDBY FWDGT suspend option in standby mode status bit FWDGT suspend option in standby mode status bit 0: FWDGT is suspend in system standby mode 1: FWDGT is running in system standby mode. 18 1 FWDGSPD_DPSLP FWDGT suspend option in deepsleep mode status bit FWDGT suspend option in deepsleep mode status bit 0: FWDGT is suspend in system deepsleep mode 1: FWDGT is running in system deepsleep mode. 17 1 SPC[7:0] Security protection level option byte status bits Security protection level option byte status bits 0xAA: No protection 0xCC: Protection level high Any value except 0xAA or 0xCC: Protection level low. 8 8 nRST_STDBY Option byte standby reset status bit Option byte standby reset status bit 0: Generates a reset instead of entering standby mode 1: No reset when entering standby mode. 7 1 nRST_DPSLP Option byte deepsleep reset status bit Option byte deepsleep reset status bit 0: Generates a reset instead of entering Deep-sleep mode 1: No reset when entering Deep-sleep mode 6 1 nWDG_HW Watchdog status bit Watchdog status bit 0: Hardware free watchdog 1: Software free watchdog 4 1 BOR_TH[1:0] BOR threshold status bits BOR threshold status bits 00: No BOR function 01: BOR threshold value 1 10: BOR threshold value 2 11: BOR threshold value 3 2 2 FMC_OBSTAT0_MDF FMC_OBSTAT0_MDF 0x04 0x20 read-write 0x01C6AAD0 FFFF IOSPDOPEN Allowed enable configuration bit for I/O speed optimization at low-voltage Allowed enable configuration bit for I/O speed optimization at low-voltage. 0: Chip operating voltage greater than 2.5V, so I/O speed optimization is not allowed 1: Chip operating voltage is less than 2.5V, so I/O speed optimization is allowed 29 1 DTCM1ECCEN DTCM1 ECC function enable configuration bit DTCM1 ECC function enable configuration bit 0: Disabled CPU DTCM1 ECC function 1: Enabled CPU DTCM1 ECC function 24 1 DTCM0ECCEN DTCM0 ECC function enable configuration bit DTCM0 ECC function enable configuration bit 0: Disabled CPU DTCM0 ECC function 1: enabled CPU DTCM0 ECC function 23 1 ITCMECCEN ITCM ECC function enable configuration bit ITCM ECC function enable configuration bit 0: disabled CPU ITCM ECC function 1: enabled CPU ITCM ECC function 22 1 SCR Secure mode configuration bit Secure mode configuration bit 0: Disable secure mode. 1: Enable secure mode. 21 1 FWDGSPD_STDBY FWDGT suspend option in standby mode configuration bit FWDGT suspend option in standby mode configuration bit 0: FWDGT is suspend in system standby mode 1: FWDGT is running in system standby mode. 18 1 FWDGSPD_DPSLP FWDGT suspend option in deepsleep mode configuration bit FWDGT suspend option in deepsleep mode configuration bit 0: FWDGT is suspend in system deepsleep mode 1: FWDGT is running in system deepsleep mode. 17 1 SPC[7:0] Security protection level option configuration bits Security protection level option configuration bits 0xAA: No protection 0xCC: Protection level high Any value except 0xAA or 0xCC: Protection level low. 8 8 nRST_STDBY Option byte standby reset configuration bit Option byte standby reset configuration bit 0: Generates a reset instead of entering standby mode 1: No reset when entering standby mode 7 1 nRST_DPSLP Option byte deepsleep reset configuration bit Option byte deepsleep reset configuration bit 0: Generates a reset instead of entering deep-sleep mode 1: No reset when entering deep-sleep mode 6 1 nWDG_HW Watchdog configuration bit Watchdog configuration bit 0: Hardware free watchdog 1: Software free watchdog 4 1 BOR_TH[1:0] BOR threshold configuration bits BOR threshold configuration bits 00: No BOR function 01: BOR threshold value 1 10: BOR threshold value 2 11: BOR threshold value 3 2 2 FMC_DCRPADDR_EFT FMC_DCRPADDR_EFT 0x0C 0x20 read 0x000000FF FFFF DCRP_EREN DCRP area erase enable status bit DCRP area erase enable status bit. 0: DCRP is not erased. 1: DCRP is erased when a SPC level low to no protection demotion or a protection-removed mass erase occur. 31 1 DCRP_AREA_END[10:0] DCRP area end address status bits DCRP area end address status bits These bits contain the last 4K-byte block of the DCRP area. End absolute address = ( DCRP_AREA_END[10:0] + 1 ) * 4096 - 1 + 0x0800_0000. If DCRP_AREA_END[10:0] = DCRP_AREA_START[10:0], DCRP protects the whole main flash block. If DCRP_AREA_END[10:0] < DCRP_AREA_START[10:0], protection is invalid. 16 11 DCRP_AREA_START[10:0] DCRP area start address status bits DCRP area start address status bits These bits contain the first 4K-byte block of the DCRP area. Start absolute address = DCRP_AREA_START[10:0] * 4096 + 0x0800_0000. If DCRP_AREA_END[10:0] = DCRP_AREA_START[10:0], DCRP protects the whole main flash block. If DCRP_AREA_END[10:0] < DCRP_AREA_START[10:0], protection is invalid. 0 11 FMC_DCRPADDR_MDF FMC_DCRPADDR_MDF 0x10 0x20 read-write 0x000000FF FFFF DCRP_EREN DCRP area erase enable configuration bit DCRP area erase enable configuration bit. 0: DCRP is not erased. 1: DCRP is erased when a SPC level low to no protection demotion or a protection-removed mass erase. 31 1 DCRP_AREA_END[10:0] DCRP area end address configuration bits DCRP area end address configuration bits These bits contain the last 4K-byte block of the DCRP area. End absolute address = ( DCRP_AREA_END[10:0] + 1 ) * 4096 - 1 + 0x0800_0000 If DCRP_AREA_END[10:0] = DCRP_AREA_START[10:0], DCRP protects the whole main flash block. If DCRP_AREA_END[10:0] < DCRP_AREA_START[10:0], protection is invalid. 16 11 DCRP_AREA_START[10:0] DCRP area start address configuration bits DCRP area start address configuration bits These bits contain the first 4K-byte block of the DCRP area. Start absolute address = DCRP_AREA_START[10:0] * 4096 + 0x0800_0000. If DCRP_AREA_END[10:0] = DCRP_AREA_START[10:0], DCRP protects the whole main flash block. If DCRP_AREA_END[10:0] < DCRP_AREA_START[10:0], protection is invalid. 0 11 FMC_SCRADDR_EFT FMC_SCRADDR_EFT 0x14 0x20 read 0x000000FF FFFF SCR_EREN Secure user area erase enable option status bit Secure user area erase enable option status bit. 0: No action 1: The secure user area is erased when a SPC level low to no protection demotion or a protection-removed mass erase. 31 1 SCR_AREA_END[10:0] Secure user area end address status bits Secure user area end address status bits These bits contain the last 4K-byte block of the secure user area. End absolute address = (SCR_AREA_END[10:0] + 1 ) * 4096 - 1 + 0x0800_0000 If SCR_AREA_END[10:0] = SCR_AREA_START[10:0], whole main flash block is secure user area. If SCR_AREA_END[10:0] < SCR_AREA_START[10:0], protection is invalid. 16 11 SCR_AREA_START[10:0] Secure user area start address status bits Secure user area start address status bits These bits contain the first 4K-byte block of the secure user area. Start absolute address = SCR_AREA_START[10:0] * 4096 + 0x0800_0000. If SCR_AREA_END[10:0] = SCR_AREA_START[10:0], whole main flash block is secure user area. If SCR_AREA_END[10:0] < SCR_AREA_START[10:0], protection is invalid. 0 11 FMC_SCRADDR_MDF FMC_SCRADDR_MDF 0x18 0x20 read-write 0x000000FF FFFF SCR_EREN Secure user area erase enable option configuration bit Secure user area erase enable option configuration bit. 0: No action 1: The secure user area is erased when a SPC level low to no protection demotion or a protection-removed mass erase. 31 1 SCR_AREA_END[10:0] Secure user area end address configuration bits Secure user area end address configuration bits These bits contain the last 4K-byte block of the secure user area. End absolute address = (SCR_AREA_END[10:0] + 1 ) * 4096 - 1 + 0x0800_0000 If SCR_AREA_END[10:0] = SCR_AREA_START[10:0], whole main flash block is secure user. If SCR_AREA_END[10:0] < SCR_AREA_START[10:0], protection is invalid. 16 11 SCR_AREA_START[10:0] Secure user area start address configuration bits Secure user area start address configuration bits These bits contain the first 4K-byte block of the secure user area. Start absolute address = SCR_AREA_START[10:0] * 4096 + 0x0800_0000. If SCR_AREA_END[10:0] = SCR_AREA_START[10:0], whole main flash block is secure user. If SCR_AREA_END[10:0] < SCR_AREA_START[10:0], protection is invalid. 0 11 FMC_WP_EFT FMC_WP_EFT 0x1C 0x20 read 0x3FFFFF FFFF WP[29] 0x8780000~0x87BFFFF WP[29] bit reflects the corresponding 64 sectors to erase/program protection status. 0: corresponding 64 sectors are erase/program protected 1: corresponding 64 sectors are not erase/program protected 29 1 WP[28] 0x8700000~0x877FFFF each bit reflects the corresponding 128 sectors to erase/program protection status. 0: corresponding 128 sectors are erase/program protected. 1: corresponding 128 sectors are not erase/program protected 28 1 WP[27] 0x8680000~0x86FFFFF each bit reflects the corresponding 128 sectors to erase/program protection status. 0: corresponding 128 sectors are erase/program protected. 1: corresponding 128 sectors are not erase/program protected 27 1 WP[26] 0x8600000~0x867FFFF each bit reflects the corresponding 128 sectors to erase/program protection status. 0: corresponding 128 sectors are erase/program protected. 1: corresponding 128 sectors are not erase/program protected 26 1 WP[25] 0x8580000~0x85FFFFF each bit reflects the corresponding 128 sectors to erase/program protection status. 0: corresponding 128 sectors are erase/program protected. 1: corresponding 128 sectors are not erase/program protected 25 1 WP[24] 0x8500000~0x857FFFF each bit reflects the corresponding 128 sectors to erase/program protection status. 0: corresponding 128 sectors are erase/program protected. 1: corresponding 128 sectors are not erase/program protected 24 1 WP[23] 0x8480000~0x84FFFFF each bit reflects the corresponding 128 sectors to erase/program protection status. 0: corresponding 128 sectors are erase/program protected. 1: corresponding 128 sectors are not erase/program protected 23 1 WP[22] 0x8400000~0x847FFFF each bit reflects the corresponding 128 sectors to erase/program protection status. 0: corresponding 128 sectors are erase/program protected. 1: corresponding 128 sectors are not erase/program protected 22 1 WP[21] 0x8380000~0x83FFFFF each bit reflects the corresponding 128 sectors to erase/program protection status. 0: corresponding 128 sectors are erase/program protected. 1: corresponding 128 sectors are not erase/program protected 21 1 WP[20] 0x8300000~0x837FFFF each bit reflects the corresponding 128 sectors to erase/program protection status. 0: corresponding 128 sectors are erase/program protected. 1: corresponding 128 sectors are not erase/program protected 20 1 WP[19] 0x8280000~0x82FFFFF each bit reflects the corresponding 128 sectors to erase/program protection status. 0: corresponding 128 sectors are erase/program protected. 1: corresponding 128 sectors are not erase/program protected 19 1 WP[18] 0x8200000~0x827FFFF each bit reflects the corresponding 128 sectors to erase/program protection status. 0: corresponding 128 sectors are erase/program protected. 1: corresponding 128 sectors are not erase/program protected 18 1 WP[17] 0x8180000~0x81FFFFF each bit reflects the corresponding 128 sectors to erase/program protection status. 0: corresponding 128 sectors are erase/program protected. 1: corresponding 128 sectors are not erase/program protected 17 1 WP[16] 0x8100000~0x817FFFF each bit reflects the corresponding 128 sectors to erase/program protection status. 0: corresponding 128 sectors are erase/program protected. 1: corresponding 128 sectors are not erase/program protected 16 1 WP[15] 0x80F0000~0x80FFFFF each bit reflects the corresponding 16 sectors to erase/program protection status. 0: corresponding 16 sectors are erase/program protected. 1: corresponding 16 sectors are not erase/program protected 15 1 WP[14] 0x80E0000~0x80EFFFF each bit reflects the corresponding 16 sectors to erase/program protection status. 0: corresponding 16 sectors are erase/program protected. 1: corresponding 16 sectors are not erase/program protected 14 1 WP[13] 0x80D0000~0x80DFFFF each bit reflects the corresponding 16 sectors to erase/program protection status. 0: corresponding 16 sectors are erase/program protected. 1: corresponding 16 sectors are not erase/program protected 13 1 WP[12] 0x80C0000~0x80CFFFF each bit reflects the corresponding 16 sectors to erase/program protection status. 0: corresponding 16 sectors are erase/program protected. 1: corresponding 16 sectors are not erase/program protected 12 1 WP[11] 0x80B0000~0x80BFFFF each bit reflects the corresponding 16 sectors to erase/program protection status. 0: corresponding 16 sectors are erase/program protected. 1: corresponding 16 sectors are not erase/program protected 11 1 WP[10] 0x80A0000~0x80AFFFF each bit reflects the corresponding 16 sectors to erase/program protection status. 0: corresponding 16 sectors are erase/program protected. 1: corresponding 16 sectors are not erase/program protected 10 1 WP[9] 0x8090000~0x809FFFF each bit reflects the corresponding 16 sectors to erase/program protection status. 0: corresponding 16 sectors are erase/program protected. 1: corresponding 16 sectors are not erase/program protected 9 1 WP[8] 0x8080000~0x808FFFF each bit reflects the corresponding 16 sectors to erase/program protection status. 0: corresponding 16 sectors are erase/program protected. 1: corresponding 16 sectors are not erase/program protected 8 1 WP[7] 0x8070000~0x807FFFF each bit reflects the corresponding 16 sectors to erase/program protection status. 0: corresponding 16 sectors are erase/program protected. 1: corresponding 16 sectors are not erase/program protected 7 1 WP[6] 0x8060000~0x806FFFF each bit reflects the corresponding 16 sectors to erase/program protection status. 0: corresponding 16 sectors are erase/program protected. 1: corresponding 16 sectors are not erase/program protected 6 1 WP[5] 0x8050000~0x805FFFF each bit reflects the corresponding 16 sectors to erase/program protection status. 0: corresponding 16 sectors are erase/program protected. 1: corresponding 16 sectors are not erase/program protected 5 1 WP[4] 0x8040000~0x804FFFF each bit reflects the corresponding 16 sectors to erase/program protection status. 0: corresponding 16 sectors are erase/program protected. 1: corresponding 16 sectors are not erase/program protected 4 1 WP[3] 0x8030000~0x803FFFF each bit reflects the corresponding 16 sectors to erase/program protection status. 0: corresponding 16 sectors are erase/program protected. 1: corresponding 16 sectors are not erase/program protected 3 1 WP[2] 0x8020000~0x802FFFF each bit reflects the corresponding 16 sectors to erase/program protection status. 0: corresponding 16 sectors are erase/program protected. 1: corresponding 16 sectors are not erase/program protected 2 1 WP[1] 0x8010000~0x801FFFF each bit reflects the corresponding 16 sectors to erase/program protection status. 0: corresponding 16 sectors are erase/program protected. 1: corresponding 16 sectors are not erase/program protected 1 1 WP[0] 0x8000000~0x800FFFF each bit reflects the corresponding 16 sectors to erase/program protection status. 0: corresponding 16 sectors are erase/program protected. 1: corresponding 16 sectors are not erase/program protected 0 1 FMC_WP_MDF FMC_WP_MDF 0x20 0x20 read-write 0x3FFFFF FFFF WP[29] 0x8780000~0x87BFFFF WP[29] bit reflects the corresponding 64 sectors to erase/program protection status. 0: corresponding 64 sectors are erase/program protected 1: corresponding 64 sectors are not erase/program protected 29 1 WP[28] 0x8700000~0x877FFFF each bit reflects the corresponding 128 sectors to erase/program protection status. 0: corresponding 128 sectors are erase/program protected. 1: corresponding 128 sectors are not erase/program protected 28 1 WP[27] 0x8680000~0x86FFFFF each bit reflects the corresponding 128 sectors to erase/program protection status. 0: corresponding 128 sectors are erase/program protected. 1: corresponding 128 sectors are not erase/program protected 27 1 WP[26] 0x8600000~0x867FFFF each bit reflects the corresponding 128 sectors to erase/program protection status. 0: corresponding 128 sectors are erase/program protected. 1: corresponding 128 sectors are not erase/program protected 26 1 WP[25] 0x8580000~0x85FFFFF each bit reflects the corresponding 128 sectors to erase/program protection status. 0: corresponding 128 sectors are erase/program protected. 1: corresponding 128 sectors are not erase/program protected 25 1 WP[24] 0x8500000~0x857FFFF each bit reflects the corresponding 128 sectors to erase/program protection status. 0: corresponding 128 sectors are erase/program protected. 1: corresponding 128 sectors are not erase/program protected 24 1 WP[23] 0x8480000~0x84FFFFF each bit reflects the corresponding 128 sectors to erase/program protection status. 0: corresponding 128 sectors are erase/program protected. 1: corresponding 128 sectors are not erase/program protected 23 1 WP[22] 0x8400000~0x847FFFF each bit reflects the corresponding 128 sectors to erase/program protection status. 0: corresponding 128 sectors are erase/program protected. 1: corresponding 128 sectors are not erase/program protected 22 1 WP[21] 0x8380000~0x83FFFFF each bit reflects the corresponding 128 sectors to erase/program protection status. 0: corresponding 128 sectors are erase/program protected. 1: corresponding 128 sectors are not erase/program protected 21 1 WP[20] 0x8300000~0x837FFFF each bit reflects the corresponding 128 sectors to erase/program protection status. 0: corresponding 128 sectors are erase/program protected. 1: corresponding 128 sectors are not erase/program protected 20 1 WP[19] 0x8280000~0x82FFFFF each bit reflects the corresponding 128 sectors to erase/program protection status. 0: corresponding 128 sectors are erase/program protected. 1: corresponding 128 sectors are not erase/program protected 19 1 WP[18] 0x8200000~0x827FFFF each bit reflects the corresponding 128 sectors to erase/program protection status. 0: corresponding 128 sectors are erase/program protected. 1: corresponding 128 sectors are not erase/program protected 18 1 WP[17] 0x8180000~0x81FFFFF each bit reflects the corresponding 128 sectors to erase/program protection status. 0: corresponding 128 sectors are erase/program protected. 1: corresponding 128 sectors are not erase/program protected 17 1 WP[16] 0x8100000~0x817FFFF each bit reflects the corresponding 128 sectors to erase/program protection status. 0: corresponding 128 sectors are erase/program protected. 1: corresponding 128 sectors are not erase/program protected 16 1 WP[15] 0x80F0000~0x80FFFFF each bit reflects the corresponding 16 sectors to erase/program protection status. 0: corresponding 16 sectors are erase/program protected. 1: corresponding 16 sectors are not erase/program protected 15 1 WP[14] 0x80E0000~0x80EFFFF each bit reflects the corresponding 16 sectors to erase/program protection status. 0: corresponding 16 sectors are erase/program protected. 1: corresponding 16 sectors are not erase/program protected 14 1 WP[13] 0x80D0000~0x80DFFFF each bit reflects the corresponding 16 sectors to erase/program protection status. 0: corresponding 16 sectors are erase/program protected. 1: corresponding 16 sectors are not erase/program protected 13 1 WP[12] 0x80C0000~0x80CFFFF each bit reflects the corresponding 16 sectors to erase/program protection status. 0: corresponding 16 sectors are erase/program protected. 1: corresponding 16 sectors are not erase/program protected 12 1 WP[11] 0x80B0000~0x80BFFFF each bit reflects the corresponding 16 sectors to erase/program protection status. 0: corresponding 16 sectors are erase/program protected. 1: corresponding 16 sectors are not erase/program protected 11 1 WP[10] 0x80A0000~0x80AFFFF each bit reflects the corresponding 16 sectors to erase/program protection status. 0: corresponding 16 sectors are erase/program protected. 1: corresponding 16 sectors are not erase/program protected 10 1 WP[9] 0x8090000~0x809FFFF each bit reflects the corresponding 16 sectors to erase/program protection status. 0: corresponding 16 sectors are erase/program protected. 1: corresponding 16 sectors are not erase/program protected 9 1 WP[8] 0x8080000~0x808FFFF each bit reflects the corresponding 16 sectors to erase/program protection status. 0: corresponding 16 sectors are erase/program protected. 1: corresponding 16 sectors are not erase/program protected 8 1 WP[7] 0x8070000~0x807FFFF each bit reflects the corresponding 16 sectors to erase/program protection status. 0: corresponding 16 sectors are erase/program protected. 1: corresponding 16 sectors are not erase/program protected 7 1 WP[6] 0x8060000~0x806FFFF each bit reflects the corresponding 16 sectors to erase/program protection status. 0: corresponding 16 sectors are erase/program protected. 1: corresponding 16 sectors are not erase/program protected 6 1 WP[5] 0x8050000~0x805FFFF each bit reflects the corresponding 16 sectors to erase/program protection status. 0: corresponding 16 sectors are erase/program protected. 1: corresponding 16 sectors are not erase/program protected 5 1 WP[4] 0x8040000~0x804FFFF each bit reflects the corresponding 16 sectors to erase/program protection status. 0: corresponding 16 sectors are erase/program protected. 1: corresponding 16 sectors are not erase/program protected 4 1 WP[3] 0x8030000~0x803FFFF each bit reflects the corresponding 16 sectors to erase/program protection status. 0: corresponding 16 sectors are erase/program protected. 1: corresponding 16 sectors are not erase/program protected 3 1 WP[2] 0x8020000~0x802FFFF each bit reflects the corresponding 16 sectors to erase/program protection status. 0: corresponding 16 sectors are erase/program protected. 1: corresponding 16 sectors are not erase/program protected 2 1 WP[1] 0x8010000~0x801FFFF each bit reflects the corresponding 16 sectors to erase/program protection status. 0: corresponding 16 sectors are erase/program protected. 1: corresponding 16 sectors are not erase/program protected 1 1 WP[0] 0x8000000~0x800FFFF each bit reflects the corresponding 16 sectors to erase/program protection status. 0: corresponding 16 sectors are erase/program protected. 1: corresponding 16 sectors are not erase/program protected 0 1 FMC_BTADDR_EFT FMC_BTADDR_EFT 0x24 0x20 read 0x1FF00800 FFFF BOOT_ADDR1[15:0] Boot address 1 status bits Boot address 1 status bits MSB of the boot address if BOOT pin is high. 16 16 BOOT_ADDR0[15:0] Boot address 0 status bits Boot address 0 status bits MSB of the boot address if BOOT pin is low. 0 16 FMC_BTADDR_MDF FMC_BTADDR_MDF 0x28 0x20 read-write 0x1FF00800 FFFF BOOT_ADDR1[15:0] Boot address 1 configuration bits Boot address 1 configuration bits. Configure the MSB of boot address if the BOOT pin is high. 16 16 BOOT_ADDR0[15:0] Boot address 0 configuration bits Boot address 0 configuration bits. Configure the MSB of the boot address if the BOOT pin is low. 0 16 FMC_OBSTAT1_EFT FMC_OBSTAT1_EFT 0x34 0x20 read 0x00000087 FFFF DATA[15:0] User defined option byte data status value User defined option byte data status value 16 16 DTCM_SZ_SHRRAM[3:0] DTCM size of shared RAM status bits DTCM size of shared RAM status bits. DTCM + ITCM can not be more than 512Kbyte 0000: 0-byte DTCM; 0111: 64-Kbyte DTCM 1000: 128-Kbyte DTCM; 1001: 256-Kbyte DTCM 1010: 512-Kbyte DTCM 4 4 ITCM_SZ_SHRRAM[3:0] ITCM size of shared RAM status bits ITCM size of shared RAM status bits. DTCM + ITCM can not be more than 512Kbyte 0000: 0-byte ITCM; 0111: 64-Kbyte ITCM 1000: 128-Kbyte ITCM; 1001: 256-Kbyte ITCM 1010: 512-Kbyte ITCM 0 4 FMC_OBSTAT1_MDF FMC_OBSTAT1_MDF 0x38 0x20 read-write 0x00000087 FFFF DATA[15:0] User defined option byte data configuration value User defined option byte data configuration value 16 16 DTCM_SZ_SHRRAM[3:0] DTCM size of shared RAM configuration bits DTCM size of shared RAM configuration bits. DTCM + ITCM can not be more than 512Kbyte 0000: 0-byte DTCM; 0111: 64-Kbyte DTCM 1000: 128-Kbyte DTCM; 1001: 256-Kbyte DTCM 1010: 512-Kbyte DTCM 4 4 ITCM_SZ_SHRRAM[3:0] ITCM size of shared RAM configuration bits ITCM size of shared RAM configuration bits. DTCM + ITCM can not be more than 512Kbyte 0000: 0-byte ITCM; 0111: 64-Kbyte ITCM 1000: 128-Kbyte ITCM; 1001: 256-Kbyte ITCM 1010: 512-Kbyte ITCM 0 4 EFUSE_USER_CTL EFUSE_USER_CTL 0x0 0x20 read-write FFFF SCR_AREA_END[7:0] Secure user area end address bits Secure user area end address bits These bits contain the last 32K-byte block of the secure user area. The secure user area can be defined by efuse with a granularity of 32 Kbytes. End absolute address = ( SCR_AREA_END[7:0] + 1) * 32768 - 1 + 0x0800_0000. If SCR_AREA_END[7:0] = SCR_AREA_START[7:0] = 0 , the secure user area is undefined. If SCR_AREA_END[7:0] = SCR_AREA_START[7:0] > 0 , whole main flash block is secure user. If SCR_AREA_END[7:0] < SCR_AREA_START[7:0], secure user area is invalid. Refer to Table 36. Secure user area configuration for more details. 24 8 SCR_AREA_START[7:0] Secure user area start address bits Secure user area start address bits These bits contain the first 32K-byte block of the secure user area. The secure user area can be defined by efuse with a granularity of 32 Kbytes. Start absolute address = SCR_AREA_START[7:0] * 32768 + 0x0800_0000. If SCR_AREA_END[7:0] = SCR_AREA_START[7:0] = 0 , the secure user area is undefined. If SCR_AREA_END[7:0] = SCR_AREA_START[7:0] > 0, whole main flash block is secure user. If SCR_AREA_END[7:0] < SCR_AREA_START[7:0], secure user area is invalid. Refer to Table 36. Secure user area configuration for more details. 16 8 SCR Secure mode enable Secure mode enable 0: Disable secure mode. 1: Enable secure mode. 13 1 SPC_H Configure security protection to level high Configure security protection to level high Refer to Table 34. SPC protection level configuration for more details. 12 1 SPC_L Configure security protection to level low Configure security protection to level low Refer to Table 34. SPC protection level configuration for more details. 11 1 JTAGNSW SW or JTAG debugger select SW or JTAG debugger select 0: SW 1: JTAG 10 1 NDBG[1:0] Debugging permission setting Debugging permission setting 00: Normal JTAG ( only valid when JTAGNSW bit is 1, otherwise SW debugger is selected ) 01: Secure JTAG ( only valid when JTAGNSW bit is 1, otherwise SW debugger is selected ) 10~11: No debug ( debug function is closed regardless of the JTAGNSW bit ) 8 2 UDLK EFUSE_USER_DATAx register lock bit EFUSE_USER_DATAx register lock bit 0: Unlock EFUSE_USER_DATAx register, the register can be modified. 1: Lock EFUSE_USER_DATAx register, the register can not be modified. 4 1 AESEN Lock EFUSE_AES_KEYx register and enable AES decrypt function Lock EFUSE_AES_KEYx register and enable AES decrypt function 0: Disable AES decrypt and AES key can be written 1: Enable AES decrypt and AES key canot be written 3 1 UCLK Low 16 bits of EFUSE_USER_CTL register lock bit Low 16 bits of EFUSE_USER_CTL register lock bit 0: Unlock the low 16 bits of EFUSE_USER_CTL register, the bits can be modified 1: Lock the low 16 bits of EFUSE_USER_CTL register, the bits can not be modified If the UCLK bit is 1, other lock bits in EFUSE_USER_CTL register cannot be modified, so user should be careful when set UCLK bit. 2 1 SCRLK Secure userarea address lock bit Secure userarea address lock bit 0: Unlock the high 16 bits in EFUSE_USER_CTL register, the bits can be modified. 1: Lock the high 16 bits in EFUSE_USER_CTL register, the bits can not be modified. 1 1 DPLK EFUSE_DPx register lock bit EFUSE_DPx register lock bit. 0: Unlock EFUSE_DPx register, the register can be written or read. 1: Lock EFUSE_DPx register, the register can not be written. When this bit is 1, the JTAGNSW bit is 1, and the NDBG[1:0] bits are 2b'01 or 2b'11, the register can not be read. Otherwise this register can be read. 0 1 EFUSE_MCU_RSV EFUSE_MCU_RSV 0x04 0x20 read-write FFFF DCRP_AREA_END[7:0] DCRP area end address bits DCRP area end address bits These bits contain the last 32K-byte block of the DCRP area. The DCRP area can be defined by efuse with a granularity of 32 Kbytes. End absolute address = (DCRP_AREA_END[7:0] + 1) * 32768 - 1 + 0x0800_0000. If DCRP_AREA_END[7:0] = DCRP_AREA_START[7:0] = 0, DCRP area is undefined. If DCRP_AREA_END[7:0] = DCRP_AREA_START[7:0] > 0, whole main flash block is DCRP area. If DCRP_AREA_END[7:0] < DCRP_AREA_START[7:0], DCRP area is invalid. Refer to Table 35. DCRP area configuration for more details. 24 8 DCRP_AREA_START[7:0] DCRP area start address bits DCRP area start address bits These bits contain the first 32K-byte block of the DCRP area. The DCRP area can be defined by efuse with a granularity of 32 Kbytes. Start absolute address = DCRP_AREA_START[7:0] * 32768 + 0x0800_0000. If DCRP_AREA_END[7:0] = DCRP_AREA_START[7:0] = 0, DCRP area is undefined. If DCRP_AREA_END[7:0] = DCRP_AREA_START[7:0] > 0, whole main flash block is DCRP area. If DCRP_AREA_END[7:0] < DCRP_AREA_START[7:0], DCRP area is invalid. Refer to Table 35. DCRP area configuration for more details. 16 8 MCU_RSV[5:0] MCU reserved data MCU reserved data 10 6 DCRPLK DCRP area address lock bit DCRP area address lock bit 0: Unlock the high 16 bits in EFUSE_MCU_RSV register, the bits can be modified. 1: Lock the high 16 bits in EFUSE_MCU_RSV register, the bits can not be modified. 9 1 MCURSVLK Low 16 bits of EFUSE_MCU_RSV register lock bit Low 16 bits of EFUSE_MCU_RSV register lock bit 0: Unlock the low 16 bits of EFUSE_MCU_RSV register, the bits can be modified 1: Lock the low 16 bits of EFUSE_MCU_RSV register, the bits can not be modified If the MCURSVLK bit is 1, other lock bits in EFUSE_MCU_RSV register cannot be modified, so user should be careful when set MCURSVLK bit. 8 1 VFIMG Firmware image verification enable bit Firmware image verification enable bit 0: Disable firmware image verification 1: Enable firmware image verification 7 1 DISLFI Licensed firmware install ( LFI ) disable Licensed firmware install ( LFI ) disable 0: Enable licensed firmware install 1: Disable licensed firmware install 6 1 AESNCAU AES key for cau configuration bit AES key for cau configuration bit 0: The AES key can be used for CAU 1: The AES key cannot be used for CAU 0 1 EFUSE_DP0 EFUSE_DP0 0x08 0x20 read-write FFFF DP0[31:0] Efuse debug password value Efuse debug password value 0 32 EFUSE_DP1 EFUSE_DP1 0x0C 0x20 read-write FFFF DP1[31:0] Efuse debug password value Efuse debug password value 0 32 USERDATA0 USERDATA0 0x20 0x20 read-write FFFF USERDATA0[31:0] Efuse USER_DATA0 value Efuse USER_DATA0 value 0 32 USERDATA1 USERDATA1 0x24 0x20 read-write FFFF USERDATA1[31:0] Efuse USER_DATA1 value Efuse USER_DATA1 value 0 32 USERDATA2 USERDATA2 0x28 0x20 read-write FFFF USERDATA2[31:0] Efuse USER_DATA2 value Efuse USER_DATA2 value 0 32 USERDATA3 USERDATA3 0x2C 0x20 read-write FFFF USERDATA3[31:0] Efuse USER_DATA3 value Efuse USER_DATA3 value 0 32