FMC_OBCTL FMC_OBCTL 0x0 0x20 read-write 0xFFEFFCAA FFFF NRST_MDSEL[1:0] NRST pin mode selection NRST pin mode selection. 00: Reserved 01: A low level on the NRST pin can reset system, internal reset cannot drive NRST pin. 10: NRST pin function as normal GPIO, and only internal RESET. 11: NRST pin configure as input/output mode. 28 2 nBOOT0 BOOT0 option bit BOOT0 option bit 0: BOOT0 is 1 1: BOOT0 is 0 27 1 nSWBT0 Software BOOT0 disable Software BOOT0 disable 0: BOOT0 depends on the option bit nBOOT0 1: BOOT0 depends on PB8/BOOT0 pin 26 1 TCMSRAM_ERS TCM SRAM erase if system reset TCM SRAM erase if system reset 0: TCM SRAM erased if a system reset occurs 1: TCM SRAM is not erased if a system reset occurs 25 1 SRAM_ECCEN SRAM and TCM SRAM ECC disable SRAM and TCM SRAM ECC disable 0: SRAM and TCM SRAM ECC enable 1: SRAM and TCM SRAM ECC disable 24 1 nBOOT1 Boot1 configuration bit Boot1 configuration bit 0: BOOT1 is 1 1: BOOT1 is 0 Together with the BOOT0 pin, this bit selects boot mode 23 1 DBS Double banks or single bank selection Double banks or single bank selection. 0: Single bank mode with 128 bits width 1: Dual bank mode with 64 bits width This bit can only be written when DCRP0/1 is disabled. 22 1 BB Option byte boot bank value Option byte boot bank value 0: Boot from bank0, when configured boot from main memory 1: Boot from bank1 or bank0 if bank1 is void, (or Bootloader continues executing if bank1 and bank0 are both void, and the chip is not under security protection level high,) when configured boot from main memory. 20 1 FWDGSPD_STDBY FWDGT suspend option in standby mode configuration bit FWDGT suspend option in standby mode configuration bit 0: FWDGT is suspend in system standby mode 1: FWDGT is running in system standby mode 18 1 FWDGSPD_DPSLP FWDGT suspend option in deepsleep mode configuration bit FWDGT suspend option in deepsleep mode configuration bit 0: FWDGT is suspend in system deepsleep mode 1: FWDGT is running in system deepsleep mode. 17 1 nFWDG_HW Free watchdog configuration bit Free watchdog configuration bit 0: Hardware free watchdog 1: Software free watchdog 16 1 FMC_SWP FMC memory mapping swap FMC memory mapping swap This bit controls the address mapping swap between bank0 and bank1 of the main Flash. 0: Flash bank0 is mapped at 0x0804 0000 and Flash bank1 is mapped at 0x0800 0000 1: Flash bank0 is mapped at 0x0800 0000 and Flash bank1 is mapped at 0x0804 0000 15 1 nRST_STDBY Option byte standby reset value Option byte standby reset value 0: Generates a reset if entering standby mode 1: No reset if entering standby mode 13 1 nRST_DPSLP Option byte deepsleep reset value Option byte deepsleep reset value 0: Generates a reset if entering Deep-sleep mode 1: No reset if entering Deep-sleep mode 12 1 BOR_TH[1:0] BOR threshold status bits BOR threshold status bits. 00: BOR value 0. Reset value threshold is around 1.7 V 01: BOR value 1. Reset value threshold is around 2.0 V 10: BOR value 2. Reset value threshold is around 2.2 V 11: BOR value 3. Reset value threshold is around 2.5 V 8 2 SPC[7:0] Security protection level option byte status bits Security protection level option byte status bits 0xAA: No protection 0xCC: Protection level high Any value except 0xAA or 0xCC: Protection level low. 0 8 FMC_DCRP_SADDR0 FMC_DCRP_SADDR0 0x4 0x20 read-write 0xFFFFFFFF FFFF DCRP0_SADDR [14:0] DCRP area start address offset configuration bits for bank0 DCRP area start address offset configuration bits for bank0 DBS=1: DCRP0_SADDR contains the start address of the bank0 DCRP area. DBS=0: DCRP0_SADDR contains the start address of the first DCRP area for all memory. 0 15 FMC_DCRP_EADDR0 FMC_DCRP_EADDR0 0x8 0x20 read-write 0x00FF0000 FFFF DCRP_EREN DCRP area erase enable configuration bit DCRP area erase enable configuration bit. 0: DCRP is not erased when SPC value is decreased from low to no protection. 1: DCRP is erased when SPC value is decreased from low to no protection. 31 1 DCRP0_EADDR [14:0] DCRP area end address offset configuration bits for bank0 DCRP area end address offset configuration bits for bank0 DBS=1: DCRP0_EADDR contains the end address of the bank0 DCRP area. DBS=0: DCRP0_EADDR contains the end address of the first DCRP area for all memory. 0 15 FMC_BK0WP0 FMC_BK0WP0 0xC 0x20 read-write 0xFE00FFFF FFFF BK0WP0_EADDR[7:0] WP first area end offset WP first area end offset DBS=1: BK0WP0_EADDR[7:0] contains the last page of the WP first area in bank0. DBS=0: BK0WP0_EADDR[7:0] contains the last page of the WP first area for all memory. 16 8 BK0WP0_SADDR[7:0] WP first area start offset WP first area start offset DBS=1: BK0WP0_SADDR[7:0] contains the first page of the WP first area for bank0. DBS=0: BK0WP0_SADDR[7:0] contains the first page of the WP first area for all memory. 0 8 FMC_BK0WP1 FMC_BK0WP1 0x10 0x20 read-write 0xFE00FFFF FFFF BK0WP1_EADDR[7:0] WP second area end offset WP second area end offset DBS=1: BK0WP1_EADDR[7:0] contains the last page of the WP second area for bank0. DBS=0: BK0WP1_EADDR[7:0] contains the last page of the WP second area for all memory. 16 8 BK0WP1_SADDR[7:0] WP second area start offset WP second area start offset DBS=1: BK0WP1_SADDR[7:0] contains the first page of the WP second area for bank0. DBS=0: BK0WP1_SADDR[7:0] contains the first page of the WP second area for all memory 0 8 FMC_DCRP_SADDR1 FMC_DCRP_SADDR1 0x24 0x20 read-write 0xFFFFFFFF FFFF DCRP1_SADDR [14:0] DCRP area start address offset configuration bits for bank1 DCRP area start address offset configuration bits for bank1 DBS=1: DCRP1_SADDR contains the start address of the bank1 DCRP area. DBS=0: DCRP1_SADDR contains the start address of the second DCRP area for all memory. 0 15 FMC_DCRP_EADDR1 FMC_DCRP_EADDR1 0x28 0x20 read-write 0x00FF0000 FFFF DCRP1_EADDR [14:0] DCRP area end address offset configuration bits for bank1 DCRP area end address offset configuration bits for bank1 DBS=1: DCRP1_EADDR contains the end address of the bank1 DCRP area. DBS=0: DCRP1_EADDR contains the end address of the second DCRP area for all memory. 0 15 FMC_BK1WP0 FMC_BK1WP0 0x2C 0x20 read-write 0xFE00FFFF FFFF BK1WP0_EADDR[7:0] WP third area end offset WP third area end offset DBS=1 BK1WP0_EADDR[7:0] contains the last page of the WP first area for bank1. DBS=0 BK1WP0_EADDR[7:0] contains the last page of the WP third area for all memory 16 8 BK1WP0_SADDR[7:0] WP third area start offset WP third area start offset DBS=1 BK1WP0_SADDR[7:0] contains the first page of the WP first area for bank1. DBS=0 BK1WP0_SADDR[7:0] contains the first page of the WP third area for all memory. 0 8 FMC_BK1WP1 FMC_BK1WP1 0x30 0x20 read-write 0xFE00FFFF FFFF BK1WP1_EADDR[7:0] WP fourth area end offset WP fourth area end offset DBS=1: BK1WP1_EADDR[7:0] contains the last page of the WP second area for bank1. DBS=0: BK1WP1_EADDR[7:0] contains the last page of the WP fourth area for all memory 16 8 BK1WP1_SADDR[7:0] WP fourth area start offset WP fourth area start offset DBS=1: BK1WP1_SADDR[7:0] contains the first page of the WP second area for bank1. DBS=0: BK1WP1_SADDR[7:0] contains the first page of the WP fourth area for all memory. 0 8 FMC_BK0SCR FMC_BK0SCR 0x50 0x20 read-write 0xFF00FC00 FFFF BOOTLK This bit is set to force boot from user flash area This bit is set to force boot from user flash area. 0: Support flash, RAM and system boot 1: Only boot from main flash 16 1 SCR_PAGE_CNT0[8:0] Configure the number of pages in the bank0 secure user area Configure the number of pages in the bank0 secure user area. Secure user area starts at bank0 base address.The memory size is SCR_PAGE_CNT0 * page size. This field can be changed when SPC level is no protection only. 0 9 FMC_BK1SCR FMC_BK1SCR 0x54 0x20 read-write 0xFF00FE00 FFFF SCR_PAGE_CNT1 [8:0] Configure the number of pages in the bank1 secure user area Configure the number of pages in the bank1 secure user area. Secure user area starts at at bank1 base address.The memory size is SCR_PAGE_CNT1 * page size. This field can be changed when SPC level is no protection only. When DBS = 0, this field is useless. 0 9 OTP OTP 0x40 0x40 0x0 0x01 0x1FFF7000 0x1FFF77FF OTP_Block OTP_Block 0x1FFF7000 0x1FFF77FF 0x0 0x800 0x00 0 0