OB_SPC OB_SPC 0x0 0x8 read-write A5 FFFF OB_SPC option byte Security Protection Code option byte Security Protection Code 0xA5: No protection 0xCC: Protection level high Any value except 0xA5 or 0xCC: Protection level low. 0 8 OB_USER[7:0] OB_USER[7:0] 0x1 0x8 read-write FFFF FFFF nRST_STDBY nRST_STDBY nRST_STDBY 0: Generates a reset if entering standby mode 1: No reset if entering standby mode 6 1 nRST_DPSLP nRST_DPSLP nRST_DPSLP 0: Generates a reset if entering Deep-sleep mode 1: No reset if entering Deep-sleep mode 5 1 BORF_TH BORF_TH BORF_TH 00: BOR falling level 1 with threshold around 2.0 V 01: BOR falling level 2 with threshold around 2.2 V 10: BOR falling level 3 with threshold around 2.5 V 11: BOR falling level 4 with threshold around 2.8 V 3 2 BORR_TH BORR_TH BORR_TH 00: BOR rising level 1 with threshold around 2.1 V 01: BOR rising level 1 with threshold around 2.3 V 10: BOR rising level 1 with threshold around 2.6 V 11: BOR rising level 1 with threshold around 2.9 V 1 2 BORST_EN BORST_EN BORST_EN 0: Brown out reset disable, power-on reset defined by POR/PDR levels 1: Brown out reset enable, values of BORR_TH and BORF_TH taken into account 0 1 OB_USER[15:8] OB_USER[15:8] 0x2 0x8 read-write FFFF FFFF SRAM_ECCEN SRAM_ECCEN SRAM_ECCEN 0: SRAM ECC enable 1: SRAM ECC disable 6 1 HXTAL_REMAP HXTAL_REMAP HXTAL_REMAP 0: Remapping enable 1: Remapping disable 5 1 nWWDG_HW nWWDG_HW nWWDG_HW 0: Hardware window watchdog 1: Software window watchdog 3 1 nFWDG_HW nFWDG_HW nFWDG_HW 0: Hardware free watchdog 1: Software free watchdog 0 1 OB_USER[23:16] OB_USER[23:16] 0x3 0x8 read-write FFFF FFFF NRST_MDSEL NRST_MDSEL NRST_MDSEL 00: Reserved 01: A low level on the NRST pin can reset system, internal reset cannot drive NRST pin. 10: NRST pin function as normal GPIO, and only internal RESET. 11: NRST pin configure as input/output mode. 3 2 nBOOT0 nBOOT0 nBOOT0 0: BOOT0 signal is 1 1: BOOT0 signal is 0 2 1 nBOOT1 nBOOT1 nBOOT1 0: BOOT1 signal is 1 1: BOOT1 signal is 0 Together with the BOOT0 signal, this bit selects boot mode 1 1 SWBT0 SWBT0 SWBT0 0: BOOT0 signal depends on PA14/BOOT0 pin 1: BOOT0 signal depends on the option bit nBOOT0 0 1 OB_SPC_N OB_SPC_N 0x4 0x8 read 5A 0 OB_SPC_N OB_SPC complement value OB_SPC complement value 0 8 OB_USER_N[7:0] OB_USER_N[7:0] 0x5 0x8 read FFFF 0 OB_USER_N[7:0] OB_USER complement value bit 7 to 0 OB_USER complement value bit 7 to 0 0 8 OB_USER_N[15:8] OB_USER_N[15:8] 0x6 0x8 read FFFF 0 OB_USER_N[15:8] OB_USER complement value bit 15 to 8 OB_USER complement value bit 15 to 8 0 8 OB_USER_N[23:16] OB_USER_N[23:16] 0x7 0x8 read FFFF 0 OB_USER_N[23:16] OB_USER complement value bit 23 to 16 OB_USER complement value bit 23 to 16 0 8 DCRP0_SADDR DCRP0_SADDR 0x8 0x8 read-write 7F FFFF DCRP area 0 start address DCRP area 0 start address DCRP area 0 start address 0 7 DCRP0_SADDR_N DCRP0_SADDR_N 0xC 0x8 read FFFF 0 DCRP0_SADDR_N DCRP0_SADDR complement value bit 6 to 0 DCRP0_SADDR complement value bit 6 to 0 0 8 DCRP0_EADDR DCRP0_EADDR 0x10 0x8 read-write 0 FFFF DCRP area 0 end address DCRP area 0 end address DCRP area 0 end address 0 7 DCRP_EREN DCRP_EREN 0x13 0x8 read-write 0 FFFF 0: DCRP area is not erased when a SPC value is decreased from value 1 to value 0 0: DCRP area is not erased when a SPC value is decreased from value 1 to value 0 0: DCRP area is not erased when a SPC value is decreased from value 1 to value 0 1: DCRP area is erased when a SPC value is decreased from value 1 to value 0 7 1 DCRP0_EADDR_N DCRP0_EADDR_N 0x14 0x8 read FFFF 0 DCRP0_EADDR_N DCRP0_EADDR complement value bit 6 to 0 DCRP0_EADDR complement value bit 6 to 0 0 8 DCRP_EREN_N DCRP_EREN_N 0x17 0x8 read FFFF 0 DCRP_EREN complement value bit 7 DCRP_EREN complement value bit 7 DCRP_EREN complement value bit 7 7 1 WP0_SADDR WP0_SADDR 0x18 0x8 read-write 3F FFFF the first page of WP area 0 the first page of WP area 0 the first page of WP area 0 0 6 WP0_EADDR WP0_EADDR 0x1A 0x8 read-write 0 FFFF the last page of WP area 0 the last page of WP area 0 the last page of WP area 0 0 6 WP0_SADDR_N WP0_SADDR_N 0x1C 0x8 read FFFF 0 WP0_SADDR_N WP0_SADDR complement value bit 5 to 0 WP0_SADDR complement value bit 5 to 0 0 8 WP0_EADDR_N WP0_EADDR_N 0x1E 0x8 read FFFF 0 WP0_EADDR_N WP0_EADDR complement value bit 5 to 0 WP0_EADDR complement value bit 5 to 0 0 8 WP1_SADDR WP1_SADDR 0x20 0x8 read-write 3F FFFF the first page of WP area 1 the first page of WP area 1 the first page of WP area 1 0 6 WP1_EADDR WP1_EADDR 0x22 0x8 read-write 0 FFFF the last page of WP area 1 the last page of WP area 1 the last page of WP area 1 0 6 WP1_SADDR_N WP1_SADDR_N 0x24 0x8 read FFFF 0 WP1_SADDR_N WP1_SADDR complement value bit 5 to 0 WP1_SADDR complement value bit 5 to 0 0 8 WP1_EADDR_N WP1_EADDR_N 0x26 0x8 read FFFF 0 WP1_EADDR_N WP1_EADDR complement value bit 5 to 0 WP1_EADDR complement value bit 5 to 0 0 8 DCRP1_SADDR DCRP1_SADDR 0x28 0x8 read-write 7F FFFF DCRP area 1 start address DCRP area 1 start address DCRP area 1 start address 0 7 DCRP1_SADDR_N DCRP1_SADDR_N 0x2C 0x8 read FFFF 0 DCRP1_SADDR_N DCRP1_SADDR complement value bit 6 to 0 DCRP1_SADDR complement value bit 6 to 0 0 8 DCRP1_EADDR DCRP1_EADDR 0x30 0x8 read-write 0 FFFF DCRP1_EADDR DCRP area 1 end address DCRP1_EADDR DCRP area 1 end address DCRP1_EADDR DCRP area 1 end address 0 7 DCRP1_EADDR_N DCRP1_EADDR_N 0x34 0x8 read FFFF 0 DCRP1_EADDR complement value bit 6 to 0 DCRP1_EADDR complement value bit 6 to 0 DCRP1_EADDR complement value bit 6 to 0 0 7 SCR_PAGE_CNT SCR_PAGE_CNT 0x70 0x8 read-write 0 FFFF Configure the number of pages in secure user area. Configure the number of pages in secure user area. Configure the number of pages in secure user area. 0 7 BOOTLK BOOTLK 0x72 0x8 read-write 0 FFFF This bit is set to force boot from user flash area. This bit is set to force boot from user flash area. This bit is set to force boot from user flash area. 0: Support flash, ram and system boot 1: Only boot from main flash 0 1 SCR_PAGE_CNT_N SCR_PAGE_CNT_N 0x75 0x8 read FFFF 0 SCR_PAGE_CNT complement value bit 6 to 0 SCR_PAGE_CNT complement value bit 6 to 0 SCR_PAGE_CNT complement value bit 6 to 0 0 7 BOOTLK_N BOOTLK_N 0x77 0x8 read FFFF 0 BOOTLK_N BOOTLK complement value bit 0 BOOTLK complement value bit 0 0 8 OTP OTP 0x20 0x20 0x0 0x01 0x1FFF7000 0x1FFF73FF OTP_Block OTP_Block 0x1FFF7000 0x1FFF73FF 0x0 0x400 0x00 0 0