{ "License": [ "Copyright (C) 2023 The Android Open Source Project", "", "Licensed under the Apache License, Version 2.0 (the “License”);", "you may not use this file except in compliance with the License.", "You may obtain a copy of the License at", "", " http://www.apache.org/licenses/LICENSE-2.0", "", "Unless required by applicable law or agreed to in writing, software", "distributed under the License is distributed on an “AS IS” BASIS,", "WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.", "See the License for the specific language governing permissions and", "limitations under the License." ], "arch": "common_x86", "insns": [ { "encodings": { "Adcb": { "opcodes": [ "80", "2" ] }, "Rclb": { "opcodes": [ "C0", "2" ] }, "Rcrb": { "opcodes": [ "C0", "3" ] }, "Sbbb": { "opcodes": [ "80", "3" ] } }, "args": [ { "class": "GeneralReg8/Mem8", "usage": "use_def" }, { "class": "Imm8" }, { "class": "FLAGS", "usage": "use_def" } ] }, { "encodings": { "Adcb": { "opcode": "12" }, "Sbbb": { "opcode": "1A" } }, "args": [ { "class": "GeneralReg8", "usage": "use_def" }, { "class": "Mem8", "usage": "use" }, { "class": "FLAGS", "usage": "use_def" } ] }, { "encodings": { "Adcb": { "opcode": "10", "type": "reg_to_rm" }, "Sbbb": { "opcode": "18", "type": "reg_to_rm" } }, "args": [ { "class": "GeneralReg8/Mem8", "usage": "use_def" }, { "class": "GeneralReg8", "usage": "use" }, { "class": "FLAGS", "usage": "use_def" } ] }, { "encodings": { "AdcbAccumulator": { "opcode": "14" }, "SbbbAccumulator": { "opcode": "1C" } }, "args": [ { "class": "AL", "usage": "use_def" }, { "class": "Imm8" }, { "class": "FLAGS", "usage": "use_def" } ] }, { "encodings": { "Adcl": { "opcode": "13" }, "Sbbl": { "opcode": "1B" } }, "args": [ { "class": "GeneralReg32", "usage": "use_def" }, { "class": "Mem32", "usage": "use" }, { "class": "FLAGS", "usage": "use_def" } ] }, { "encodings": { "Adcl": { "opcodes": [ "81", "2" ] }, "Sbbl": { "opcodes": [ "81", "3" ] } }, "args": [ { "class": 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] } }, "args": [ { "class": "GeneralReg16", "usage": "use_def" }, { "class": "Mem16", "usage": "use" }, { "class": "FLAGS", "usage": "use_def" } ] }, { "encodings": { "Adcw": { "opcodes": [ "66", "81", "2" ] }, "Sbbw": { "opcodes": [ "66", "81", "3" ] } }, "args": [ { "class": "GeneralReg16/Mem16", "usage": "use_def" }, { "class": "Imm16" }, { "class": "FLAGS", "usage": "use_def" } ] }, { "encodings": { "Adcw": { "opcodes": [ "66", "11" ], "type": "reg_to_rm" }, "Sbbw": { "opcodes": [ "66", "19" ], "type": "reg_to_rm" } }, "args": [ { "class": "GeneralReg16/Mem16", "usage": "use_def" }, { "class": "GeneralReg16", "usage": "use" }, { "class": "FLAGS", "usage": "use_def" } ] }, { "encodings": { "AdcwAccumulator": { "opcodes": [ "66", "15" ] }, "SbbwAccumulator": { "opcodes": [ "66", "1D" ] } }, "args": [ { "class": "AX", "usage": "use_def" }, { "class": "Imm16" }, { "class": "FLAGS", "usage": "use_def" } ] }, { "encodings": { "AdcwImm8": { "opcodes": [ "66", "83", "2" ] }, "Rclw": { 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{ "class": "Mem8", "usage": "use" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "Addb": { "opcode": "00", "type": "reg_to_rm" }, "Andb": { "opcode": "20", "type": "reg_to_rm" }, "Orb": { "opcode": "08", "type": "reg_to_rm" }, "Subb": { "opcode": "28", "type": "reg_to_rm" }, "Xorb": { "opcode": "30", "type": "reg_to_rm" } }, "args": [ { "class": "GeneralReg8/Mem8", "usage": "use_def" }, { "class": "GeneralReg8", "usage": "use" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "AddbAccumulator": { "opcode": "04" }, "AndbAccumulator": { "opcode": "24" }, "OrbAccumulator": { "opcode": "0C" }, "SubbAccumulator": { "opcode": "2C" }, "XorbAccumulator": { "opcode": "34" } }, "args": [ { "class": "AL", "usage": "use_def" }, { "class": "Imm8" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "Addl": { "opcode": "01", "type": "reg_to_rm" }, "Andl": { "opcode": "21", "type": "reg_to_rm" }, "Btcl": { "opcodes": [ "0F", "BB" ], "type": "reg_to_rm" }, "Btrl": { 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}, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "AddlAccumulator": { "opcode": "05" }, "AndlAccumulator": { "opcode": "25" }, "OrlAccumulator": { "opcode": "0D" }, "SublAccumulator": { "opcode": "2D" }, "XorlAccumulator": { "opcode": "35" } }, "args": [ { "class": "EAX", "usage": "use_def" }, { "class": "Imm32" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "AddlImm8": { "opcodes": [ "83", "0" ] }, "AndlImm8": { "opcodes": [ "83", "4" ] }, "Btcl": { "opcodes": [ "0F", "BA", "7" ] }, "Btl": { "opcodes": [ "0F", "BA", "4" ] }, "Btrl": { "opcodes": [ "0F", "BA", "6" ] }, "Btsl": { "opcodes": [ "0F", "BA", "5" ] }, "OrlImm8": { "opcodes": [ "83", "1" ] }, "Roll": { "opcodes": [ "C1", "0" ] }, "Rorl": { "opcodes": [ "C1", "1" ] }, "Sarl": { "opcodes": [ "C1", "7" ] }, "Shll": { "opcodes": [ "C1", "4" ] }, "Shrl": { "opcodes": [ "C1", "5" ] }, "SublImm8": { "opcodes": [ "83", "5" ] }, "XorlImm8": { "opcodes": [ "83", "6" ] } }, "args": [ { "class": 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"0F", "C2", "07" ] }, "Cmpunordpd": { "opcodes": [ "66", "0F", "C2", "03" ] }, "Cmpunordps": { "opcodes": [ "0F", "C2", "03" ] }, "Divpd": { "opcodes": [ "66", "0F", "5E" ] }, "Divps": { "opcodes": [ "0F", "5E" ] }, "Haddpd": { "feature": "SSE3", "opcodes": [ "66", "0F", "7C" ] }, "Haddps": { "feature": "SSE3", "opcodes": [ "F2", "0F", "7C" ] }, "Maxpd": { "opcodes": [ "66", "0F", "5F" ] }, "Maxps": { "opcodes": [ "0F", "5F" ] }, "Minpd": { "opcodes": [ "66", "0F", "5D" ] }, "Minps": { "opcodes": [ "0F", "5D" ] }, "Mulpd": { "opcodes": [ "66", "0F", "59" ] }, "Mulps": { "opcodes": [ "0F", "59" ] }, "Orpd": { "opcodes": [ "66", "0F", "56" ] }, "Orps": { "opcodes": [ "0F", "56" ] }, "Packssdw": { "opcodes": [ "66", "0F", "6B" ] }, "Packsswb": { "opcodes": [ "66", "0F", "63" ] }, "Packusdw": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "2B" ] }, "Packuswb": { "opcodes": [ "66", "0F", "67" ] }, "Paddb": { "opcodes": [ "66", "0F", "FC" ] }, "Paddd": { "opcodes": [ "66", "0F", "FE" ] }, "Paddq": { "opcodes": [ "66", "0F", "D4" ] }, "Paddsb": { "opcodes": [ "66", "0F", "EC" ] }, "Paddsw": { "opcodes": [ "66", "0F", "ED" ] }, "Paddusb": { "opcodes": [ "66", "0F", "DC" ] }, "Paddusw": { "opcodes": [ "66", "0F", "DD" ] }, "Paddw": { "opcodes": [ "66", "0F", "FD" ] }, "Pand": { "opcodes": [ "66", "0F", "DB" ] }, "Pandn": { "opcodes": [ "66", "0F", "DF" ] }, "Pavgb": { "opcodes": [ "66", "0F", "E0" ] }, "Pavgw": { "opcodes": [ "66", "0F", "E3" ] }, "Pcmpeqb": { "opcodes": [ "66", "0F", "74" ] }, "Pcmpeqd": { "opcodes": [ "66", "0F", "76" ] }, "Pcmpeqq": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "29" ] }, "Pcmpeqw": { "opcodes": [ "66", "0F", "75" ] }, "Pcmpgtb": { "opcodes": [ "66", "0F", "64" ] }, "Pcmpgtd": { "opcodes": [ "66", "0F", "66" ] }, "Pcmpgtq": { "feature": "SSE4_2", "opcodes": [ "66", "0F", "38", "37" ] }, "Pcmpgtw": { "opcodes": [ "66", "0F", "65" ] }, "Phaddd": { "feature": "SSSE3", "opcodes": [ "66", "0F", "38", "02" ] }, "Phaddw": { "feature": "SSSE3", "opcodes": [ "66", "0F", "38", "01" ] }, "Pmaxsb": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "3C" ] }, "Pmaxsd": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "3D" ] }, "Pmaxsw": { "opcodes": [ "66", "0F", "EE" ] }, "Pmaxub": { "opcodes": [ "66", "0F", "DE" ] }, "Pmaxud": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "3F" ] }, "Pmaxuw": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "3E" ] }, "Pminsb": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "38" ] }, "Pminsd": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "39" ] }, "Pminsw": { "opcodes": [ "66", "0F", "EA" ] }, "Pminub": { "opcodes": [ "66", "0F", "DA" ] }, "Pminud": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "3B" ] }, "Pminuw": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "3A" ] }, "Pmulhrsw": { "feature": "SSSE3", "opcodes": [ "66", "0F", "38", "0B" ] }, "Pmulhw": { "opcodes": [ "66", "0F", "E5" ] }, "Pmulld": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "40" ] }, "Pmullw": { "opcodes": [ "66", "0F", "D5" ] }, "Pmuludq": { "opcodes": [ "66", "0F", "F4" ] }, "Por": { "opcodes": [ "66", "0F", "EB" ] }, "Psadbw": { "opcodes": [ "66", "0F", "F6" ] }, "Pshufb": { "feature": "SSSE3", "opcodes": [ "66", "0F", "38", "00" ] }, "Pslld": { "opcodes": [ "66", "0F", "F2" ] }, "Psllq": { "opcodes": [ "66", "0F", "F3" ] }, "Psllw": { "opcodes": [ "66", "0F", "F1" ] }, "Psrad": { "opcodes": [ "66", "0F", "E2" ] }, "Psraw": { "opcodes": [ "66", "0F", "E1" ] }, "Psrld": { "opcodes": [ "66", "0F", "D2" ] }, "Psrlq": { "opcodes": [ "66", "0F", "D3" ] }, "Psrlw": { "opcodes": [ "66", "0F", "D1" ] }, "Psubb": { "opcodes": [ "66", "0F", "F8" ] }, "Psubd": { "opcodes": [ "66", "0F", "FA" ] }, "Psubq": { "opcodes": [ "66", "0F", "FB" ] }, "Psubsb": { "opcodes": [ "66", "0F", "E8" ] }, "Psubsw": { "opcodes": [ "66", "0F", "E9" ] }, "Psubusb": { "opcodes": [ "66", "0F", "D8" ] }, "Psubusw": { "opcodes": [ "66", "0F", "D9" ] }, "Psubw": { "opcodes": [ "66", "0F", "F9" ] }, "Punpckhbw": { "opcodes": [ "66", "0F", "68" ] }, "Punpckhdq": { "opcodes": [ "66", "0F", "6A" ] }, "Punpckhqdq": { "opcodes": [ "66", "0F", "6D" ] }, "Punpckhwd": { "opcodes": [ "66", "0F", "69" ] }, "Punpcklbw": { "opcodes": [ "66", "0F", "60" ] }, "Punpckldq": { "opcodes": [ "66", "0F", "62" ] }, "Punpcklqdq": { "opcodes": [ "66", "0F", "6C" ] }, "Punpcklwd": { "opcodes": [ "66", "0F", "61" ] }, "Pxor": { "opcodes": [ "66", "0F", "EF" ] }, "Rsqrtps": { "opcodes": [ "0F", "52" ] }, "Subpd": { "opcodes": [ "66", "0F", "5C" ] }, "Subps": { "opcodes": [ "0F", "5C" ] }, "Vrsqrtps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "52" ] }, "Xorpd": { "opcodes": [ "66", "0F", "57" ] }, "Xorps": { "opcodes": [ "0F", "57" ] } }, "args": [ { "class": "VecReg128", "usage": "use_def" }, { "class": "VecReg128/VecMem128", "usage": "use" } ] }, { "encodings": { "Addsd": { "opcodes": [ "F2", "0F", "58" ] }, "Cmpeqsd": { "opcodes": [ "F2", "0F", "C2", "00" ] }, "Cmplesd": { "opcodes": [ "F2", "0F", "C2", "02" ] }, "Cmpltsd": { "opcodes": [ "F2", "0F", "C2", "01" ] }, "Cmpneqsd": { "opcodes": [ "F2", "0F", "C2", "04" ] }, "Cmpnlesd": { "opcodes": [ "F2", "0F", "C2", "06" ] }, "Cmpnltsd": { "opcodes": [ "F2", "0F", "C2", "05" ] }, "Cmpordsd": { "opcodes": [ "F2", "0F", "C2", "07" ] }, "Cmpunordsd": { "opcodes": [ "F2", "0F", "C2", "03" ] }, "Divsd": { "opcodes": [ "F2", "0F", "5E" ] }, "Mulsd": { "opcodes": [ "F2", "0F", "59" ] }, "Subsd": { "opcodes": [ "F2", "0F", "5C" ] } }, "args": [ { "class": "FpReg64", "usage": "use_def" }, { "class": "FpReg64/VecMem64", "usage": "use" } ] }, { "encodings": { "Addss": { "opcodes": [ "F3", "0F", "58" ] }, "Cmpeqss": { "opcodes": [ "F3", "0F", "C2", "00" ] }, "Cmpless": { "opcodes": [ "F3", "0F", "C2", "02" ] }, "Cmpltss": { "opcodes": [ "F3", "0F", "C2", "01" ] }, "Cmpneqss": { "opcodes": [ "F3", "0F", "C2", "04" ] }, "Cmpnless": { "opcodes": [ "F3", "0F", "C2", "06" ] }, "Cmpnltss": { "opcodes": [ "F3", "0F", "C2", "05" ] }, "Cmpordss": { "opcodes": [ "F3", "0F", "C2", "07" ] }, "Cmpunordss": { "opcodes": [ "F3", "0F", "C2", "03" ] }, "Divss": { "opcodes": [ "F3", "0F", "5E" ] }, "Mulss": { "opcodes": [ "F3", "0F", "59" ] }, "Subss": { "opcodes": [ "F3", "0F", "5C" ] } }, "args": [ { "class": "FpReg32", "usage": "use_def" }, { "class": "FpReg32/VecMem32", "usage": "use" } ] }, { "encodings": { "Addw": { "opcodes": [ "66", "01" ], "type": "reg_to_rm" }, "Andw": { "opcodes": [ "66", "21" ], "type": "reg_to_rm" }, "Btcw": { "opcodes": [ "66", "0F", "BB" ], "type": "reg_to_rm" }, "Btrw": { "opcodes": [ "66", "0F", "B3" ], "type": "reg_to_rm" }, "Btsw": { "opcodes": [ "66", "0F", "AB" ], "type": "reg_to_rm" }, "Orw": { "opcodes": [ "66", "09" ], "type": "reg_to_rm" }, "Subw": { "opcodes": [ "66", "29" ], "type": "reg_to_rm" }, "Xorw": { "opcodes": [ "66", "31" ], "type": "reg_to_rm" } }, "args": [ { "class": "GeneralReg16/Mem16", "usage": "use_def" }, { "class": "GeneralReg16", "usage": "use" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "Addw": { "opcodes": [ "66", "03" ] }, "Andw": { "opcodes": [ "66", "23" ] }, "Orw": { "opcodes": [ "66", "0B" ] }, "Subw": { "opcodes": [ "66", "2B" ] }, "Xorw": { "opcodes": [ "66", "33" ] } }, "args": [ { "class": "GeneralReg16", "usage": "use_def" }, { "class": "Mem16", "usage": "use" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "Addw": { "opcodes": [ "66", "81", "0" ] }, "Andw": { "opcodes": [ "66", "81", "4" ] }, "Orw": { "opcodes": [ "66", "81", "1" ] }, "Subw": { "opcodes": [ "66", "81", "5" ] }, "Xorw": { "opcodes": [ "66", "81", "6" ] } }, "args": [ { "class": "GeneralReg16/Mem16", "usage": "use_def" }, { "class": "Imm16" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "AddwAccumulator": { "opcodes": [ "66", "05" ] }, "AndwAccumulator": { "opcodes": [ "66", "25" ] }, "OrwAccumulator": { "opcodes": [ "66", "0D" ] }, "SubwAccumulator": { "opcodes": [ "66", "2D" ] }, "XorwAccumulator": { "opcodes": [ "66", "35" ] } }, "args": [ { "class": "AX", "usage": "use_def" }, { "class": "Imm16" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "AddwImm8": { "opcodes": [ "66", "83", "0" ] }, "AndwImm8": { "opcodes": [ "66", "83", "4" ] }, "OrwImm8": { "opcodes": [ "66", "83", "1" ] }, "Rolw": { "opcodes": [ "66", "C1", "0" ] }, "Rorw": { "opcodes": [ "66", "C1", "1" ] }, "Sarw": { "opcodes": [ "66", "C1", "7" ] }, "Shlw": { "opcodes": [ "66", "C1", "4" ] }, "Shrw": { "opcodes": [ "66", "C1", "5" ] }, "SubwImm8": { "opcodes": [ "66", "83", "5" ] }, "XorwImm8": { "opcodes": [ "66", "83", "6" ] } }, "args": [ { "class": "GeneralReg16/Mem16", "usage": "use_def" }, { "class": "Imm8" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "Andnl": { "feature": "BMI", "opcodes": [ "C4", "02", "00", "F2" ], "type": "vex_rm_to_reg" } }, "args": [ { "class": "GeneralReg32", "usage": "def" }, { "class": "GeneralReg32", "usage": "use" }, { "class": "GeneralReg32/Mem32", "usage": "use" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "Bextrl": { "feature": "BMI", "opcodes": [ "C4", "02", "00", "F7" ] }, "Bzhil": { "feature": "BMI2", "opcodes": [ "C4", "02", "00", "F5" ] } }, "args": [ { "class": "GeneralReg32", "usage": "use_def" }, { "class": "GeneralReg32/Mem32", "usage": "use" }, { "class": "GeneralReg32", "usage": "use" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "Blsil": { "feature": "BMI", "opcodes": [ "C4", "02", "00", "F3", "3" ], "type": "rm_to_vex" }, "Blsmskl": { "feature": "BMI", "opcodes": [ "C4", "02", "00", "F3", "2" ], "type": "rm_to_vex" }, "Blsrl": { "feature": "BMI", "opcodes": [ "C4", "02", "00", "F3", "1" ], "type": "rm_to_vex" }, "Bsfl": { "opcodes": [ "0F", "BC" ] }, "Bsrl": { "opcodes": [ "0F", "BD" ] }, "Lzcntl": { "feature": "LZCNT", "opcodes": [ "F3", "0F", "BD" ] }, "Popcntl": { "feature": "POPCNT", "opcodes": [ "F3", "0F", "B8" ] }, "Tzcntl": { "feature": "BMI", "opcodes": [ "F3", "0F", "BC" ] } }, "args": [ { "class": "GeneralReg32", "usage": "def" }, { "class": "GeneralReg32/Mem32", "usage": "use" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "Bsfw": { "opcodes": [ "66", "0F", "BC" ] }, "Bsrw": { "opcodes": [ "66", "0F", "BD" ] }, "Lzcntw": { "feature": "LZCNT", "opcodes": [ "66", "F3", "0F", "BD" ] }, "Popcntw": { "feature": "POPCNT", "opcodes": [ "66", "F3", "0F", "B8" ] }, "Tzcntw": { "feature": "BMI", "opcodes": [ "66", "F3", "0F", "BC" ] } }, "args": [ { "class": "GeneralReg16", "usage": "def" }, { "class": "GeneralReg16/Mem16", "usage": "use" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "Bswapl": { "opcodes": [ "0F", "C8" ] } }, "args": [ { "class": "GeneralReg32", "usage": "use_def" } ] }, { "encodings": { "Btl": { "opcodes": [ "0F", "A3" ], "type": "reg_to_rm" }, "Cmpl": { "opcode": "39", "type": "reg_to_rm" }, "Testl": { "opcode": "85", "type": "reg_to_rm" } }, "args": [ { "class": "GeneralReg32/Mem32", "usage": "use" }, { "class": "GeneralReg32", "usage": "use" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "Btw": { "opcodes": [ "66", "0F", "A3" ], "type": "reg_to_rm" }, "Cmpw": { "opcodes": [ "66", "39" ], "type": "reg_to_rm" }, "Testw": { "opcodes": [ "66", "85" ], "type": "reg_to_rm" } }, "args": [ { "class": "GeneralReg16/Mem16", "usage": "use" }, { "class": "GeneralReg16", "usage": "use" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "Call": { "opcodes": [ "FF", "02" ] }, "Push": { "opcode": "50" } }, "args": [ { "class": "RSP", "usage": "use_def" }, { "class": "GeneralReg", "usage": "use" } ] }, { "stems": [ "Call" ], "args": [ { "class": "RSP", "usage": "use_def" }, { "class": "Label" } ] }, { "encodings": { "Cbtw": { "opcodes": [ "66", "98" ] }, "Cbw": { "opcodes": [ "66", "98" ] } }, "args": [ { "class": "AL", "usage": "use" }, { "class": "AX", "usage": "def" } ] }, { "encodings": { "Cdq": { "opcode": "99" }, "Cltd": { "opcode": "99" } }, "args": [ { "class": "EAX", "usage": "use" }, { "class": "EDX", "usage": "def" } ] }, { "encodings": { "Clc": { "opcode": "F8" }, "Cmc": { "opcode": "F5" }, "Stc": { "opcode": "F9" } }, "args": [ { "class": "FLAGS", "usage": "use_def" } ] }, { "encodings": { "Cmovl": { "opcodes": [ "0F", "40" ] } }, "args": [ { "class": "Cond" }, { "class": "GeneralReg32", "usage": "use_def" }, { "class": "GeneralReg32/Mem32", "usage": "use" }, { "class": "FLAGS", "usage": "use" } ] }, { "encodings": { "Cmovw": { "opcodes": [ "66", "0F", "40" ] } }, "args": [ { "class": "Cond" }, { "class": "GeneralReg16", "usage": "use_def" }, { "class": "GeneralReg16/Mem16", "usage": "use" }, { "class": "FLAGS", "usage": "use" } ] }, { "encodings": { "CmpXchg8b": { "opcodes": [ "0F", "C7", "1" ] }, "Lock CmpXchg8b": { "opcodes": [ "F0", "0F", "C7", "1" ] } }, "args": [ { "class": "EAX", "usage": "use_def" }, { "class": "EDX", "usage": "use_def" }, { "class": "EBX", "usage": "use" }, { "class": "ECX", "usage": "use" }, { "class": "VecMem64", "usage": "use_def" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "CmpXchgl": { "opcodes": [ "0F", "B1" ], "type": "reg_to_rm" } }, "args": [ { "class": "EAX", "usage": "use_def" }, { "class": "GeneralReg32/Mem32", "usage": "use_def" }, { "class": "GeneralReg32", "usage": "use" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "Cmpb": { "opcodes": [ "80", "7" ] }, "Testb": { "opcodes": [ "F6", "0" ] } }, "args": [ { "class": "GeneralReg8/Mem8", "usage": "use" }, { "class": "Imm8" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "Cmpb": { "opcode": "38", "type": "reg_to_rm" }, "Testb": { "opcode": "84", "type": "reg_to_rm" } }, "args": [ { "class": "GeneralReg8/Mem8", "usage": "use" }, { "class": "GeneralReg8", "usage": "use" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "Cmpb": { "opcode": "3A" } }, "args": [ { "class": "GeneralReg8", "usage": "use" }, { "class": "Mem8", "usage": "use" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "CmpbAccumulator": { "opcode": "3C" }, "TestbAccumulator": { "opcode": "A8" } }, "args": [ { "class": "AL", "usage": "use" }, { "class": "Imm8" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "Cmpl": { "opcodes": [ "81", "7" ] }, "Testl": { "opcodes": [ "F7", "0" ] } }, "args": [ { "class": "GeneralReg32/Mem32", "usage": "use" }, { "class": "Imm32" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "Cmpl": { "opcode": "3B" } }, "args": [ { "class": "GeneralReg32", "usage": "use" }, { "class": "Mem32", "usage": "use" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "CmplAccumulator": { "opcode": "3D" }, "TestlAccumulator": { "opcode": "A9" } }, "args": [ { "class": "EAX", "usage": "use" }, { "class": "Imm32" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "CmplImm8": { "opcodes": [ "83", "7" ] } }, "args": [ { "class": "GeneralReg32/Mem32", "usage": "use" }, { "class": "Imm8" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "Cmpw": { "opcodes": [ "66", "81", "7" ] }, "Testw": { "opcodes": [ "66", "F7", "0" ] } }, "args": [ { "class": "GeneralReg16/Mem16", "usage": "use" }, { "class": "Imm16" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "Cmpw": { "opcodes": [ "66", "3B" ] } }, "args": [ { "class": "GeneralReg16", "usage": "use" }, { "class": "Mem16", "usage": "use" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "CmpwAccumulator": { "opcodes": [ "66", "3D" ] }, "TestwAccumulator": { "opcodes": [ "66", "A9" ] } }, "args": [ { "class": "AX", "usage": "use" }, { "class": "Imm16" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "CmpwImm8": { "opcodes": [ "66", "83", "7" ] } }, "args": [ { "class": "GeneralReg16/Mem16", "usage": "use" }, { "class": "Imm8" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "Cvtdq2pd": { "opcodes": [ "F3", "0F", "E6" ] }, "Cvtdq2ps": { "opcodes": [ "0F", "5B" ] }, "Cvtpd2dq": { "opcodes": [ "F2", "0F", "E6" ] }, "Cvtpd2ps": { "opcodes": [ "66", "0F", "5A" ] }, "Cvtps2dq": { "opcodes": [ "66", "0F", "5B" ] }, "Cvtps2pd": { "opcodes": [ "0F", "5A" ] }, "Cvttpd2dq": { "opcodes": [ "66", "0F", "E6" ] }, "Cvttps2dq": { "opcodes": [ "F3", "0F", "5B" ] }, "Vcvtdq2pd": { "feature": "AVX", "opcodes": [ "C4", "01", "02", "E6" ] }, "Vcvtdq2ps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "5B" ] }, "Vcvtpd2dq": { "feature": "AVX", "opcodes": [ "C4", "01", "03", "E6" ] }, "Vcvtpd2ps": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "5A" ] }, "Vcvtps2dq": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "5B" ] }, "Vcvtps2pd": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "5A" ] }, "Vcvttpd2dq": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "E6" ] }, "Vcvttps2dq": { "feature": "AVX", "opcodes": [ "C4", "01", "02", "5B" ] } }, "args": [ { "class": "VecReg128", "usage": "def" }, { "class": "VecReg128/VecMem128", "usage": "use" } ] }, { "encodings": { "Cvtsd2sil": { "opcodes": [ "F2", "0F", "2D" ] }, "Cvttsd2sil": { "opcodes": [ "F2", "0F", "2C" ] }, "Vcvtsd2sil": { "feature": "AVX", "opcodes": [ "C4", "01", "03", "2D" ] }, "Vcvttsd2sil": { "feature": "AVX", "opcodes": [ "C4", "01", "03", "2C" ] } }, "args": [ { "class": "GeneralReg32", "usage": "def" }, { "class": "FpReg64/VecMem64", "usage": "use" } ] }, { "encodings": { "Cvtsd2ss": { "opcodes": [ "F2", "0F", "5A" ] } }, "args": [ { "class": "FpReg32", "usage": "def" }, { "class": "FpReg64/VecMem64", "usage": "use" } ] }, { "encodings": { "Cvtsi2sdl": { "opcodes": [ "F2", "0F", "2A" ] } }, "args": [ { "class": "FpReg64", "usage": "def" }, { "class": "GeneralReg32/Mem32", "usage": "use" } ] }, { "encodings": { "Cvtsi2ssl": { "opcodes": [ "F3", "0F", "2A" ] } }, "args": [ { "class": "FpReg32", "usage": "def" }, { "class": "GeneralReg32/Mem32", "usage": "use" } ] }, { "encodings": { "Cvtss2sd": { "opcodes": [ "F3", "0F", "5A" ] } }, "args": [ { "class": "FpReg64", "usage": "def" }, { "class": "FpReg32/VecMem32", "usage": "use" } ] }, { "encodings": { "Cvtss2sil": { "opcodes": [ "F3", "0F", "2D" ] }, "Cvttss2sil": { "opcodes": [ "F3", "0F", "2C" ] }, "Vcvtss2sil": { "feature": "AVX", "opcodes": [ "C4", "01", "02", "2D" ] }, "Vcvttss2sil": { "feature": "AVX", "opcodes": [ "C4", "01", "02", "2C" ] } }, "args": [ { "class": "GeneralReg32", "usage": "def" }, { "class": "FpReg32/VecMem32", "usage": "use" } ] }, { "encodings": { "Cwd": { "opcodes": [ "66", "99" ] }, "Cwtd": { "opcodes": [ "66", "99" ] } }, "args": [ { "class": "AX", "usage": "use" }, { "class": "DX", "usage": "def" } ] }, { "encodings": { "Cwde": { "opcode": "98" }, "Cwtl": { "opcode": "98" } }, "args": [ { "class": "AX", "usage": "use" }, { "class": "EAX", "usage": "def" } ] }, { "encodings": { "Decb": { "opcodes": [ "FE", "1" ] }, "Incb": { "opcodes": [ "FE", "0" ] }, "Negb": { "opcodes": [ "F6", "3" ] }, "RolbByOne": { "opcodes": [ "D0", "0" ] }, "RorbByOne": { "opcodes": [ "D0", "1" ] }, "SarbByOne": { "opcodes": [ "D0", "7" ] }, "ShlbByOne": { "opcodes": [ "D0", "4" ] }, "ShrbByOne": { "opcodes": [ "D0", "5" ] } }, "args": [ { "class": "GeneralReg8/Mem8", "usage": "use_def" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "Decl": { "opcodes": [ "FF", "1" ] }, "Incl": { "opcodes": [ "FF", "0" ] } }, "args": [ { "class": "Mem32", "usage": "use_def" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "Decw": { "opcodes": [ "66", "FF", "1" ] }, "Incw": { "opcodes": [ "66", "FF", "0" ] } }, "args": [ { "class": "Mem16", "usage": "use_def" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "Divb": { "opcodes": [ "F6", "6" ] }, "Idivb": { "opcodes": [ "F6", "7" ] } }, "args": [ { "class": "AX", "usage": "use_def" }, { "class": "GeneralReg8/Mem8", "usage": "use" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "Divl": { "opcodes": [ "F7", "6" ] }, "Idivl": { "opcodes": [ "F7", "7" ] } }, "args": [ { "class": "EAX", "usage": "use_def" }, { "class": "EDX", "usage": "use_def" }, { "class": "GeneralReg32/Mem32", "usage": "use" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "Divw": { "opcodes": [ "66", "F7", "6" ] }, "Idivw": { "opcodes": [ "66", "F7", "7" ] } }, "args": [ { "class": "AX", "usage": "use_def" }, { "class": "DX", "usage": "use_def" }, { "class": "GeneralReg16/Mem16", "usage": "use" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "F2xm1": { "opcodes": [ "D9", "F0" ] }, "Fabs": { "opcodes": [ "D9", "E1" ] }, "Fchs": { "opcodes": [ "D9", "E0" ] }, "Fcos": { "opcodes": [ "D9", "FF" ] }, "Frndint": { "opcodes": [ "D9", "FC" ] }, "Fscale": { "opcodes": [ "D9", "FD" ] }, "Fsin": { "opcodes": [ "D9", "FE" ] }, "Fsqrt": { "opcodes": [ "D9", "FA" ] }, "Ftst": { "opcodes": [ "D9", "E4" ] } }, "args": [ { "class": "ST", "usage": "use_def" } ] }, { "encodings": { "FaddFromSt": { "opcodes": [ "DC", "0" ] }, "FaddpFromSt": { "opcodes": [ "DE", "0" ] }, "FdivFromSt": { "opcodes": [ "DC", "6" ] }, "FdivpFromSt": { "opcodes": [ "DE", "6" ] }, "FdivrFromSt": { "opcodes": [ "DC", "7" ] }, "FdivrpFromSt": { "opcodes": [ "DE", "7" ] }, "FmulFromSt": { "opcodes": [ "DC", "1" ] }, "FmulpFromSt": { "opcodes": [ "DE", "1" ] }, "FsubFromSt": { "opcodes": [ "DC", "4" ] }, "FsubpFromSt": { "opcodes": [ "DE", "4" ] }, "FsubrFromSt": { "opcodes": [ "DC", "5" ] }, "FsubrpFromSt": { "opcodes": [ "DE", "5" ] } }, "args": [ { "class": "RegX87", "usage": "use_def" }, { "class": "ST", "usage": "use" } ] }, { "encodings": { "FaddToSt": { "opcodes": [ "D8", "0" ] }, "FdivToSt": { "opcodes": [ "D8", "6" ] }, "FdivrToSt": { "opcodes": [ "D8", "7" ] }, "FmulToSt": { "opcodes": [ "D8", "1" ] }, "FsubToSt": { "opcodes": [ "D8", "4" ] }, "FsubrToSt": { "opcodes": [ "D8", "5" ] } }, "args": [ { "class": "ST", "usage": "use_def" }, { "class": "RegX87", "usage": "use" } ] }, { "encodings": { "Faddl": { "opcodes": [ "DC", "0" ] }, "Fdivl": { "opcodes": [ "DC", "6" ] }, "Fdivrl": { "opcodes": [ "DC", "7" ] }, "Fmull": { "opcodes": [ "DC", "1" ] }, "Fsubl": { "opcodes": [ "DC", "4" ] }, "Fsubrl": { "opcodes": [ "DC", "5" ] } }, "args": [ { "class": "ST", "usage": "use_def" }, { "class": "MemX8764", "usage": "use" } ] }, { "encodings": { "Fadds": { "opcodes": [ "D8", "0" ] }, "Fdivrs": { "opcodes": [ "D8", "7" ] }, "Fdivs": { "opcodes": [ "D8", "6" ] }, "Fiaddl": { "opcodes": [ "DA", "0" ] }, "Fidivl": { "opcodes": [ "DA", "6" ] }, "Fidivrl": { "opcodes": [ "DA", "7" ] }, "Fimull": { "opcodes": [ "DA", "1" ] }, "Fisubl": { "opcodes": [ "DA", "4" ] }, "Fisubrl": { "opcodes": [ "DA", "5" ] }, "Fmuls": { "opcodes": [ "D8", "1" ] }, "Fsubrs": { "opcodes": [ "D8", "5" ] }, "Fsubs": { "opcodes": [ "D8", "4" ] } }, "args": [ { "class": "ST", "usage": "use_def" }, { "class": "MemX8732", "usage": "use" } ] }, { "encodings": { "Fbld": { "opcodes": [ "DF", "4" ] }, "Fldt": { "opcodes": [ "DB", "5" ] } }, "args": [ { "class": "ST", "usage": "def" }, { "class": "MemX8780", "usage": "use" } ] }, { "encodings": { "Fbstp": { "opcodes": [ "DF", "6" ] }, "Fstpt": { "opcodes": [ "DB", "7" ] } }, "args": [ { "class": "MemX8780", "usage": "def" }, { "class": "ST", "usage": "use" } ] }, { "encodings": { "FcmovbToSt": { "opcodes": [ "DA", "0" ] }, "FcmovbeToSt": { "opcodes": [ "DA", "2" ] }, "FcmoveToSt": { "opcodes": [ "DA", "1" ] }, "FcmovnbToSt": { "opcodes": [ "DB", "0" ] }, "FcmovnbeToSt": { "opcodes": [ "DB", "2" ] }, "FcmovneToSt": { "opcodes": [ "DB", "1" ] }, "FcmovnuToSt": { "opcodes": [ "DB", "3" ] }, "FcmovuToSt": { "opcodes": [ "DA", "3" ] } }, "args": [ { "class": "ST", "usage": "use_def" }, { "class": "RegX87", "usage": "use" }, { "class": "FLAGS", "usage": "use" } ] }, { "encodings": { "Fcom": { "opcodes": [ "D8", "2" ] }, "Fcomp": { "opcodes": [ "D8", "3" ] }, "Fucom": { "opcodes": [ "DD", "4" ] }, "Fucomp": { "opcodes": [ "DD", "5" ] } }, "args": [ { "class": "ST", "usage": "use" }, { "class": "RegX87", "usage": "use" }, { "class": "CC", "usage": "def" } ] }, { "encodings": { "Fcomi": { "opcodes": [ "DB", "6" ] }, "Fcomip": { "opcodes": [ "DF", "6" ] }, "Fucomi": { "opcodes": [ "DB", "5" ] }, "Fucomip": { "opcodes": [ "DF", "5" ] } }, "args": [ { "class": "ST", "usage": "use" }, { "class": "RegX87", "usage": "use" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "Fcoml": { "opcodes": [ "DC", "2" ] }, "Fcompl": { "opcodes": [ "DC", "3" ] } }, "args": [ { "class": "ST", "usage": "use" }, { "class": "MemX8764", "usage": "use" }, { "class": "CC", "usage": "def" } ] }, { "encodings": { "Fcompp": { "opcodes": [ "DE", "D9" ] }, "Fucompp": { "opcodes": [ "DA", "E9" ] } }, "args": [ { "class": "ST", "usage": "use" }, { "class": "ST1", "usage": "use" }, { "class": "CC", "usage": "def" } ] }, { "encodings": { "Fcomps": { "opcodes": [ "D8", "3" ] }, "Fcoms": { "opcodes": [ "D8", "2" ] }, "Ficoml": { "opcodes": [ "DA", "2" ] }, "Ficompl": { "opcodes": [ "DA", "3" ] } }, "args": [ { "class": "ST", "usage": "use" }, { "class": "MemX8732", "usage": "use" }, { "class": "CC", "usage": "def" } ] }, { "encodings": { "Fdecstp": { "opcodes": [ "D9", "F6" ] }, "Fincstp": { "opcodes": [ "D9", "F7" ] }, "Fnop": { "opcodes": [ "D9", "D0" ] }, "Fwait": { "opcode": "9B" }, "Int3": { "opcode": "CC" }, "Lfence": { "opcodes": [ "0F", "AE", "E8" ] }, "Mfence": { "opcodes": [ "0F", "AE", "F0" ] }, "Sfence": { "opcodes": [ "0F", "AE", "F8" ] }, "Nop": { "opcode": "90" }, "UD2": { "opcodes": [ "0F", "0B" ] }, "Wait": { "opcode": "9B" } }, "args": [] }, { "encodings": { "Ffree": { "opcodes": [ "DD", "0" ] } }, "args": [ { "class": "RegX87", "usage": "use" } ] }, { "encodings": { "Fiadds": { "opcodes": [ "DE", "0" ] }, "Fidivrs": { "opcodes": [ "DE", "7" ] }, "Fidivs": { "opcodes": [ "DE", "6" ] }, "Fimuls": { "opcodes": [ "DE", "1" ] }, "Fisubrs": { "opcodes": [ "DE", "5" ] }, "Fisubs": { "opcodes": [ "DE", "4" ] } }, "args": [ { "class": "ST", "usage": "use_def" }, { "class": "MemX8716", "usage": "use" } ] }, { "encodings": { "Ficomps": { "opcodes": [ "DE", "3" ] }, "Ficoms": { "opcodes": [ "DE", "2" ] } }, "args": [ { "class": "ST", "usage": "use" }, { "class": "MemX8716", "usage": "use" }, { "class": "CC", "usage": "def" } ] }, { "encodings": { "Fildl": { "opcodes": [ "DB", "0" ] }, "Flds": { "opcodes": [ "D9", "0" ] } }, "args": [ { "class": "ST", "usage": "def" }, { "class": "MemX8732", "usage": "use" } ] }, { "encodings": { "Fildll": { "opcodes": [ "DF", "5" ] }, "Fldl": { "opcodes": [ "DD", "0" ] } }, "args": [ { "class": "ST", "usage": "def" }, { "class": "MemX8764", "usage": "use" } ] }, { "encodings": { "Filds": { "opcodes": [ "DF", "0" ] } }, "args": [ { "class": "ST", "usage": "def" }, { "class": "MemX8716", "usage": "use" } ] }, { "encodings": { "Fistl": { "opcodes": [ "DB", "2" ] }, "Fistpl": { "opcodes": [ "DB", "3" ] }, "Fisttpl": { "feature": "SSE3", "opcodes": [ "DB", "1" ] }, "Fstps": { "opcodes": [ "D9", "3" ] }, "Fsts": { "opcodes": [ "D9", "2" ] } }, "args": [ { "class": "MemX8732", "usage": "def" }, { "class": "ST", "usage": "use" } ] }, { "encodings": { "Fistpll": { "opcodes": [ "DF", "7" ] }, "Fisttpll": { "feature": "SSE3", "opcodes": [ "DD", "1" ] }, "Fstl": { "opcodes": [ "DD", "2" ] }, "Fstpl": { "opcodes": [ "DD", "3" ] } }, "args": [ { "class": "MemX8764", "usage": "def" }, { "class": "ST", "usage": "use" } ] }, { "encodings": { "Fistps": { "opcodes": [ "DF", "3" ] }, "Fists": { "opcodes": [ "DF", "2" ] }, "Fisttps": { "feature": "SSE3", "opcodes": [ "DF", "1" ] } }, "args": [ { "class": "MemX8716", "usage": "def" }, { "class": "ST", "usage": "use" } ] }, { "encodings": { "Fld1": { "opcodes": [ "D9", "E8" ] }, "Fldl2e": { "opcodes": [ "D9", "EA" ] }, "Fldl2t": { "opcodes": [ "D9", "E9" ] }, "Fldlg2": { "opcodes": [ "D9", "EC" ] }, "Fldln2": { "opcodes": [ "D9", "ED" ] }, "Fldpi": { "opcodes": [ "D9", "EB" ] }, "Fldz": { "opcodes": [ "D9", "EE" ] } }, "args": [ { "class": "ST", "usage": "use_def" } ] }, { "encodings": { "Fld": { "opcodes": [ "D9", "0" ] } }, "args": [ { "class": "ST", "usage": "def" }, { "class": "RegX87", "usage": "use" } ] }, { "encodings": { "Fldcw": { "opcodes": [ "D9", "5" ] } }, "args": [ { "class": "CC", "usage": "def" }, { "class": "MemX8732", "usage": "use" } ] }, { "encodings": { "Fldenv": { "opcodes": [ "D9", "4" ] }, "Frstor": { "opcodes": [ "DD", "4" ] }, "Fxrstor": { "opcodes": [ "0F", "AE", "1" ] } }, "args": [ { "class": "MemX87", "usage": "use" }, { "class": "CC", "usage": "def" } ] }, { "encodings": { "Fnclex": { "opcodes": [ "DB", "E2" ] }, "Fndisi": { "opcodes": [ "DB", "E1" ] }, "Fneni": { "opcodes": [ "DB", "E0" ] }, "Fninit": { "opcodes": [ "DB", "E3" ] }, "Fnsetpm": { "opcodes": [ "DB", "E4" ] } }, "args": [ { "class": "CC", "usage": "def" } ] }, { "encodings": { "Fnsave": { "opcodes": [ "DD", "6" ] }, "Fnstenv": { "opcodes": [ "D9", "6" ] }, "Fxsave": { "opcodes": [ "0F", "AE", "0" ] } }, "args": [ { "class": "CC", "usage": "def" }, { "class": "MemX87", "usage": "use" } ] }, { "encodings": { "Fnstcw": { "opcodes": [ "D9", "7" ] } }, "args": [ { "class": "MemX8732", "usage": "def" }, { "class": "CC", "usage": "use" } ] }, { "encodings": { "Fnstsw": { "opcodes": [ "DF", "E0" ] } }, "args": [ { "class": "AX", "usage": "def" }, { "class": "SW", "usage": "use" } ] }, { "encodings": { "Fnstsw": { "opcodes": [ "DD", "7" ] } }, "args": [ { "class": "MemX8732", "usage": "def" }, { "class": "SW", "usage": "use" } ] }, { "encodings": { "Fpatan": { "opcodes": [ "D9", "F3" ] }, "Fprem": { "opcodes": [ "D9", "F8" ] }, "Fprem1": { "opcodes": [ "D9", "F5" ] }, "Fyl2x": { "opcodes": [ "D9", "F1" ] }, "Fyl2xp1": { "opcodes": [ "D9", "F9" ] } }, "args": [ { "class": "ST", "usage": "use_def" }, { "class": "ST1", "usage": "use" } ] }, { "encodings": { "Fptan": { "opcodes": [ "D9", "F2" ] }, "Fsincos": { "opcodes": [ "D9", "FB" ] }, "Fxtract": { "opcodes": [ "D9", "F4" ] } }, "args": [ { "class": "ST", "usage": "use_def" }, { "class": "ST1", "usage": "def" } ] }, { "encodings": { "Fst": { "opcodes": [ "DD", "2" ] }, "Fstp": { "opcodes": [ "DD", "3" ] } }, "args": [ { "class": "RegX87", "usage": "def" }, { "class": "ST", "usage": "use" } ] }, { "encodings": { "Fxam": { "opcodes": [ "D9", "E5" ] } }, "args": [ { "class": "ST", "usage": "use" }, { "class": "CC", "usage": "def" } ] }, { "encodings": { "Fxch": { "opcodes": [ "D9", "1" ] } }, "args": [ { "class": "RegX87", "usage": "use_def" }, { "class": "ST", "usage": "use_def" } ] }, { "encodings": { "Imulb": { "opcodes": [ "F6", "5" ] }, "Mulb": { "opcodes": [ "F6", "4" ] } }, "args": [ { "class": "AL", "usage": "use" }, { "class": "AX", "usage": "def" }, { "class": "GeneralReg8/Mem8", "usage": "use" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "Imull": { "opcodes": [ "F7", "5" ] }, "Mull": { "opcodes": [ "F7", "4" ] } }, "args": [ { "class": "EAX", "usage": "use_def" }, { "class": "EDX", "usage": "def" }, { "class": "GeneralReg32/Mem32", "usage": "use" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "Imull": { "opcode": "69" } }, "args": [ { "class": "GeneralReg32", "usage": "def" }, { "class": "GeneralReg32/Mem32", "usage": "use" }, { "class": "Imm32" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "Imull": { "opcodes": [ "0F", "AF" ] } }, "args": [ { "class": "GeneralReg32", "usage": "use_def" }, { "class": "GeneralReg32/Mem32", "usage": "use" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "ImullImm8": { "opcode": "6B" } }, "args": [ { "class": "GeneralReg32", "usage": "def" }, { "class": "GeneralReg32/Mem32", "usage": "use" }, { "class": "Imm8" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "Imulw": { "opcodes": [ "66", "F7", "5" ] }, "Mulw": { "opcodes": [ "66", "F7", "4" ] } }, "args": [ { "class": "AX", "usage": "use_def" }, { "class": "DX", "usage": "def" }, { "class": "GeneralReg16/Mem16", "usage": "use" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "Imulw": { "opcodes": [ "66", "69" ] } }, "args": [ { "class": "GeneralReg16", "usage": "def" }, { "class": "GeneralReg16/Mem16", "usage": "use" }, { "class": "Imm16" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "Imulw": { "opcodes": [ "66", "0F", "AF" ] } }, "args": [ { "class": "GeneralReg16", "usage": "use_def" }, { "class": "GeneralReg16/Mem16", "usage": "use" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "ImulwImm8": { "opcodes": [ "66", "6B" ] } }, "args": [ { "class": "GeneralReg16", "usage": "def" }, { "class": "GeneralReg16/Mem16", "usage": "use" }, { "class": "Imm8" }, { "class": "FLAGS", "usage": "def" } ] }, { "stems": [ "Jcc" ], "args": [ { "class": "Cond" }, { "class": "Label" }, { "class": "FLAGS", "usage": "use" } ] }, { "stems": [ "Jmp" ], "args": [ { "class": "Label" } ] }, { "encodings": { "Jmp": { "opcodes": [ "FF", "4" ] } }, "args": [ { "class": "GeneralReg", "usage": "use" } ] }, { "encodings": { "Lahf": { "opcode": "9F" } }, "args": [ { "class": "EAX", "usage": "use_def" }, { "class": "FLAGS", "usage": "use" } ], "comment": "Use use_def below because LAHF writes to AH while preserving the rest of RAX" }, { "encodings": { "Ldmxcsr": { "opcodes": [ "0F", "AE", "2" ] }, "Vldmxcsr": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "AE", "2" ] } }, "args": [ { "class": "Mem32", "usage": "use" } ] }, { "encodings": { "Leal": { "opcode": "8D" } }, "args": [ { "class": "GeneralReg32", "usage": "def" }, { "class": "Mem", "usage": "use" } ] }, { "encodings": { "Lock CmpXchgb": { "opcodes": [ "F0", "0F", "B0" ], "type": "reg_to_rm" } }, "args": [ { "class": "AL", "usage": "use_def" }, { "class": "Mem8", "usage": "use_def" }, { "class": "GeneralReg8", "usage": "use" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "Lock CmpXchgl": { "opcodes": [ "F0", "0F", "B1" ], "type": "reg_to_rm" } }, "args": [ { "class": "EAX", "usage": "use_def" }, { "class": "Mem32", "usage": "use_def" }, { "class": "GeneralReg32", "usage": "use" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "Lock CmpXchgw": { "opcodes": [ "F0", "66", "0F", "B1" ], "type": "reg_to_rm" } }, "args": [ { "class": "AX", "usage": "use_def" }, { "class": "Mem16", "usage": "use_def" }, { "class": "GeneralReg16", "usage": "use" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "Movapd": { "opcodes": [ "66", "0F", "29" ] }, "Movaps": { "opcodes": [ "0F", "29" ] }, "Vmovapd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "29" ] }, "Vmovaps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "29" ] } }, "args": [ { "class": "VecMem128", "usage": "def" }, { "class": "XmmReg", "usage": "use" } ] }, { "encodings": { "Movapd": { "opcodes": [ "66", "0F", "28" ] }, "Movaps": { "opcodes": [ "0F", "28" ] } }, "args": [ { "class": "XmmReg", "usage": "def" }, { "class": "XmmReg/VecMem128", "usage": "use" } ] }, { "encodings": { "Movb": { "opcode": "B0" } }, "args": [ { "class": "GeneralReg8", "usage": "def" }, { "class": "Imm8" } ] }, { "encodings": { "Movb": { "opcode": "8A" } }, "args": [ { "class": "GeneralReg8", "usage": "def" }, { "class": "Mem8", "usage": "use" } ] }, { "encodings": { "Movb": { "opcode": "88", "type": "reg_to_rm" } }, "args": [ { "class": "GeneralReg8/Mem8", "usage": "def" }, { "class": "GeneralReg8", "usage": "use" } ] }, { "encodings": { "Movb": { "opcodes": [ "C6", "0" ] } }, "args": [ { "class": "Mem8", "usage": "def" }, { "class": "Imm8" } ] }, { "encodings": { "Movd": { "opcodes": [ "66", "0F", "7E" ], "type": "reg_to_rm" }, "Vmovd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "7E" ], "type": "reg_to_rm" } }, "args": [ { "class": "GeneralReg32/Mem32", "usage": "def" }, { "class": "XmmReg", "usage": "use" } ] }, { "encodings": { "Movd": { "opcodes": [ "66", "0F", "6E" ] }, "Vmovd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "6E" ] } }, "args": [ { "class": "XmmReg", "usage": "def" }, { "class": "GeneralReg32/Mem32", "usage": "use" } ] }, { "name": "MovdqRegReg", "args": [ { "class": "XmmReg", "usage": "def" }, { "class": "XmmReg", "usage": "use" } ], "asm": "Pmov", "mnemo": "MOVDQ" }, { "encodings": { "Movdqa": { "opcodes": [ "66", "0F", "7F" ] }, "Movdqu": { "opcodes": [ "F3", "0F", "7F" ] }, "Vmovdqa": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "7F" ] }, "Vmovdqu": { "feature": "AVX", "opcodes": [ "C4", "01", "02", "7F" ] } }, "args": [ { "class": "VecMem128", "usage": "def" }, { "class": "XmmReg", "usage": "use" } ] }, { "encodings": { "Movdqa": { "opcodes": [ "66", "0F", "6F" ] }, "Movdqu": { "opcodes": [ "F3", "0F", "6F" ] } }, "args": [ { "class": "XmmReg", "usage": "def" }, { "class": "XmmReg/VecMem128", "usage": "use" } ] }, { "encodings": { "Movhlps": { "opcodes": [ "0F", "12" ] }, "Movlhps": { "opcodes": [ "0F", "16" ] }, "Movsd": { "opcodes": [ "F2", "0F", "10" ] }, "Movss": { "opcodes": [ "F3", "0F", "10" ] } }, "args": [ { "class": "XmmReg", "usage": "use_def" }, { "class": "XmmReg", "usage": "use" } ], "comment": "Upper bits (lower bits for Movlhps) are unchanged" }, { "encodings": { "Movhpd": { "opcodes": [ "66", "0F", "17" ] }, "Movhps": { "opcodes": [ "0F", "17" ] }, "Movlpd": { "opcodes": [ "66", "0F", "13" ] }, "Movlps": { "opcodes": [ "0F", "13" ] }, "Vmovhpd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "17" ] }, "Vmovhps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "17" ] }, "Vmovlpd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "13" ] }, "Vmovlps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "13" ] } }, "args": [ { "class": "VecMem64", "usage": "use_def" }, { "class": "XmmReg", "usage": "use" } ] }, { "encodings": { "Movhpd": { "opcodes": [ "66", "0F", "16" ] }, "Movhps": { "opcodes": [ "0F", "16" ] }, "Movlpd": { "opcodes": [ "66", "0F", "12" ] }, "Movlps": { "opcodes": [ "0F", "12" ] } }, "args": [ { "class": "XmmReg", "usage": "use_def" }, { "class": "VecMem64", "usage": "use" } ] }, { "encodings": { "Movl": { "opcode": "8B" } }, "args": [ { "class": "GeneralReg32", "usage": "def" }, { "class": "Mem32", "usage": "use" } ] }, { "encodings": { "Movl": { "opcode": "B8" } }, "args": [ { "class": "GeneralReg32", "usage": "def" }, { "class": "Imm32" } ] }, { "encodings": { "Movl": { "opcode": "89", "type": "reg_to_rm" } }, "args": [ { "class": "GeneralReg32/Mem32", "usage": "def" }, { "class": "GeneralReg32", "usage": "use" } ] }, { "encodings": { "Movl": { "opcodes": [ "C7", "0" ] } }, "args": [ { "class": "Mem32", "usage": "def" }, { "class": "Imm32" } ] }, { "encodings": { "Movmskpd": { "opcodes": [ "66", "0F", "50" ] }, "Movmskps": { "opcodes": [ "0F", "50" ] }, "Vmovmskpd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "50" ] }, "Vmovmskps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "50" ] } }, "args": [ { "class": "GeneralReg32", "usage": "def" }, { "class": "XmmReg", "usage": "use" } ] }, { "encodings": { "Movq": { "opcodes": [ "66", "0F", "D6" ] }, "Movsd": { "opcodes": [ "F2", "0F", "11" ] }, "Vmovq": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "D6" ] }, "Vmovsd": { "feature": "AVX", "opcodes": [ "C4", "01", "03", "11" ] } }, "args": [ { "class": "VecMem64", "usage": "def" }, { "class": "XmmReg", "usage": "use" } ] }, { "encodings": { "Movq": { "opcodes": [ "F3", "0F", "7E" ] }, "Pmovsxbw": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "20" ] }, "Pmovsxdq": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "25" ] }, "Pmovsxwd": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "23" ] }, "Pmovzxbw": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "30" ] }, "Pmovzxdq": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "35" ] }, "Pmovzxwd": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "33" ] }, "Vmovq": { "feature": "AVX", "opcodes": [ "C4", "01", "02", "7E" ] } }, "args": [ { "class": "XmmReg", "usage": "def" }, { "class": "XmmReg/VecMem64", "usage": "use" } ], "comment": "Upper bits are zero-filled for Movq/Vmovq" }, { "encodings": { "Movsd": { "opcodes": [ "F2", "0F", "10" ] }, "Vmovsd": { "feature": "AVX", "opcodes": [ "C4", "01", "03", "10" ] } }, "args": [ { "class": "XmmReg", "usage": "def" }, { "class": "VecMem64", "usage": "use" } ], "comment": "Upper bits are zero-filled" }, { "encodings": { "Movss": { "opcodes": [ "F3", "0F", "10" ] }, "Vmovss": { "feature": "AVX", "opcodes": [ "C4", "01", "02", "10" ] } }, "args": [ { "class": "XmmReg", "usage": "def" }, { "class": "VecMem32", "usage": "use" } ], "comment": "Upper bits are zero-filled" }, { "encodings": { "Movss": { "opcodes": [ "F3", "0F", "11" ] } }, "args": [ { "class": "Mem32", "usage": "def" }, { "class": "XmmReg", "usage": "use" } ] }, { "encodings": { "Movsxbl": { "opcodes": [ "0F", "BE" ] }, "Movzxbl": { "opcodes": [ "0F", "B6" ] } }, "args": [ { "class": "GeneralReg32", "usage": "def" }, { "class": "GeneralReg8/Mem8", "usage": "use" } ] }, { "encodings": { "Movsxwl": { "opcodes": [ "0F", "BF" ] }, "Movzxwl": { "opcodes": [ "0F", "B7" ] } }, "args": [ { "class": "GeneralReg32", "usage": "def" }, { "class": "GeneralReg16/Mem16", "usage": "use" } ] }, { "encodings": { "Movw": { "opcodes": [ "66", "B8" ] } }, "args": [ { "class": "GeneralReg16", "usage": "def" }, { "class": "Imm16" } ] }, { "encodings": { "Movw": { "opcodes": [ "66", "8B" ] } }, "args": [ { "class": "GeneralReg16", "usage": "def" }, { "class": "Mem16", "usage": "use" } ] }, { "encodings": { "Movw": { "opcodes": [ "66", "89" ], "type": "reg_to_rm" } }, "args": [ { "class": "GeneralReg16/Mem16", "usage": "def" }, { "class": "GeneralReg16", "usage": "use" } ] }, { "encodings": { "Movw": { "opcodes": [ "66", "C7", "0" ] } }, "args": [ { "class": "Mem16", "usage": "def" }, { "class": "Imm16" } ] }, { "encodings": { "Mulxl": { "feature": "BMI2", "opcodes": [ "C4", "02", "03", "F6" ], "type": "vex_rm_to_reg" }, "Pdepl": { "feature": "BMI2", "opcodes": [ "C4", "02", "03", "F5" ], "type": "vex_rm_to_reg" }, "Pextl": { "feature": "BMI2", "opcodes": [ "C4", "02", "02", "F5" ], "type": "vex_rm_to_reg" } }, "args": [ { "class": "GeneralReg32", "usage": "use_def" }, { "class": "GeneralReg32", "usage": "use" }, { "class": "GeneralReg32/Mem32", "usage": "use" } ] }, { "encodings": { "Negl": { "opcodes": [ "F7", "3" ] }, "RollByOne": { "opcodes": [ "D1", "0" ] }, "RorlByOne": { "opcodes": [ "D1", "1" ] }, "SarlByOne": { "opcodes": [ "D1", "7" ] }, "ShllByOne": { "opcodes": [ "D1", "4" ] }, "ShrlByOne": { "opcodes": [ "D1", "5" ] } }, "args": [ { "class": "GeneralReg32/Mem32", "usage": "use_def" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "Negw": { "opcodes": [ "66", "F7", "3" ] }, "RolwByOne": { "opcodes": [ "66", "D1", "0" ] }, "RorwByOne": { "opcodes": [ "66", "D1", "1" ] }, "SarwByOne": { "opcodes": [ "66", "D1", "7" ] }, "ShlwByOne": { "opcodes": [ "66", "D1", "4" ] }, "ShrwByOne": { "opcodes": [ "66", "D1", "5" ] } }, "args": [ { "class": "GeneralReg16/Mem16", "usage": "use_def" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "Notb": { "opcodes": [ "F6", "2" ] } }, "args": [ { "class": "GeneralReg8/Mem8", "usage": "use_def" } ] }, { "encodings": { "Notl": { "opcodes": [ "F7", "2" ] } }, "args": [ { "class": "GeneralReg32/Mem32", "usage": "use_def" } ] }, { "encodings": { "Notw": { "opcodes": [ "66", "F7", "2" ] } }, "args": [ { "class": "GeneralReg16/Mem16", "usage": "use_def" } ] }, { "encodings": { "Pextrb": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "3A", "14" ], "type": "reg_to_rm" }, "Pextrd": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "3A", "16" ], "type": "reg_to_rm" }, "Pextrw": { "opcodes": [ "66", "0F", "C5" ] }, "Vpextrb": { "feature": "AVX", "opcodes": [ "C4", "03", "01", "14" ], "type": "reg_to_rm" }, "Vpextrd": { "feature": "AVX", "opcodes": [ "C4", "03", "01", "16" ], "type": "reg_to_rm" }, "Vpextrw": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "C5" ] } }, "args": [ { "class": "GeneralReg32", "usage": "def" }, { "class": "VecReg128", "usage": "use" }, { "class": "Imm8" } ] }, { "encodings": { "Pinsrb": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "3A", "20" ] }, "Pinsrd": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "3A", "22" ] }, "Pinsrw": { "opcodes": [ "66", "0F", "C4" ] } }, "args": [ { "class": "VecReg128", "usage": "use_def" }, { "class": "GeneralReg32", "usage": "use" }, { "class": "Imm8" } ] }, { "encodings": { "Pmovmskb": { "opcodes": [ "66", "0F", "D7" ] }, "Vpmovmskb": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "D7" ] } }, "args": [ { "class": "GeneralReg32", "usage": "def" }, { "class": "VecReg128", "usage": "use" } ] }, { "encodings": { "Pmovsxbd": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "21" ] }, "Pmovsxwq": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "24" ] }, "Pmovzxbd": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "31" ] }, "Pmovzxwq": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "34" ] } }, "args": [ { "class": "XmmReg", "usage": "def" }, { "class": "XmmReg/VecMem32", "usage": "use" } ] }, { "encodings": { "Pop": { "opcode": "58" } }, "args": [ { "class": "RSP", "usage": "use_def" }, { "class": "GeneralReg", "usage": "def" } ] }, { "encodings": { "Pshufd": { "opcodes": [ "66", "0F", "70" ] }, "Pshufhw": { "opcodes": [ "F3", "0F", "70" ] }, "Pshuflw": { "opcodes": [ "F2", "0F", "70" ] }, "Roundpd": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "3A", "09" ] }, "Roundps": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "3A", "08" ] }, "Vpshufd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "70" ] }, "Vpshufhw": { "feature": "AVX", "opcodes": [ "C4", "01", "02", "70" ] }, "Vpshuflw": { "feature": "AVX", "opcodes": [ "C4", "01", "03", "70" ] }, "Vroundpd": { "feature": "AVX", "opcodes": [ "C4", "03", "01", "09" ] }, "Vroundps": { "feature": "AVX", "opcodes": [ "C4", "03", "01", "08" ] } }, "args": [ { "class": "VecReg128", "usage": "def" }, { "class": "VecReg128/VecMem128", "usage": "use" }, { "class": "Imm8" } ] }, { "encodings": { "Pslld": { "opcodes": [ "66", "0F", "72", "6" ] }, "Pslldq": { "opcodes": [ "66", "0F", "73", "7" ] }, "Psllq": { "opcodes": [ "66", "0F", "73", "6" ] }, "Psllw": { "opcodes": [ "66", "0F", "71", "6" ] }, "Psrad": { "opcodes": [ "66", "0F", "72", "4" ] }, "Psraw": { "opcodes": [ "66", "0F", "71", "4" ] }, "Psrld": { "opcodes": [ "66", "0F", "72", "2" ] }, "Psrldq": { "opcodes": [ "66", "0F", "73", "3" ] }, "Psrlq": { "opcodes": [ "66", "0F", "73", "2" ] }, "Psrlw": { "opcodes": [ "66", "0F", "71", "2" ] } }, "args": [ { "class": "VecReg128", "usage": "use_def" }, { "class": "Imm8" } ] }, { "encodings": { "Push": { "opcode": "68" } }, "args": [ { "class": "RSP", "usage": "use_def" }, { "class": "Imm32" } ] }, { "encodings": { "PushImm8": { "opcode": "6A" } }, "args": [ { "class": "RSP", "usage": "use_def" }, { "class": "Imm8" } ] }, { "encodings": { "RclbByCl": { "opcodes": [ "D2", "2" ] }, "RcrbByCl": { "opcodes": [ "D2", "3" ] } }, "args": [ { "class": "GeneralReg8/Mem8", "usage": "use_def" }, { "class": "CL", "usage": "use" }, { "class": "FLAGS", "usage": "use_def" } ] }, { "encodings": { "RclbByOne": { "opcodes": [ "D0", "2" ] }, "RcrbByOne": { "opcodes": [ "D0", "3" ] } }, "args": [ { "class": "GeneralReg8/Mem8", "usage": "use_def" }, { "class": "FLAGS", "usage": "use_def" } ] }, { "encodings": { "RcllByCl": { "opcodes": [ "D3", "2" ] }, "RcrlByCl": { "opcodes": [ "D3", "3" ] } }, "args": [ { "class": "GeneralReg32/Mem32", "usage": "use_def" }, { "class": "CL", "usage": "use" }, { "class": "FLAGS", "usage": "use_def" } ] }, { "encodings": { "RcllByOne": { "opcodes": [ "D1", "2" ] }, "RcrlByOne": { "opcodes": [ "D1", "3" ] } }, "args": [ { "class": "GeneralReg32/Mem32", "usage": "use_def" }, { "class": "FLAGS", "usage": "use_def" } ] }, { "encodings": { "RclwByCl": { "opcodes": [ "66", "D3", "2" ] }, "RcrwByCl": { "opcodes": [ "66", "D3", "3" ] } }, "args": [ { "class": "GeneralReg16/Mem16", "usage": "use_def" }, { "class": "CL", "usage": "use" }, { "class": "FLAGS", "usage": "use_def" } ] }, { "encodings": { "RclwByOne": { "opcodes": [ "66", "D1", "2" ] }, "RcrwByOne": { "opcodes": [ "66", "D1", "3" ] } }, "args": [ { "class": "GeneralReg16/Mem16", "usage": "use_def" }, { "class": "FLAGS", "usage": "use_def" } ] }, { "encodings": { "Ret": { "opcode": "C3" } }, "args": [ { "class": "RSP", "usage": "use_def" } ] }, { "encodings": { "RolbByCl": { "opcodes": [ "D2", "0" ] }, "RorbByCl": { "opcodes": [ "D2", "1" ] }, "SarbByCl": { "opcodes": [ "D2", "7" ] }, "ShlbByCl": { "opcodes": [ "D2", "4" ] }, "ShrbByCl": { "opcodes": [ "D2", "5" ] } }, "args": [ { "class": "GeneralReg8/Mem8", "usage": "use_def" }, { "class": "CL", "usage": "use" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "RollByCl": { "opcodes": [ "D3", "0" ] }, "RorlByCl": { "opcodes": [ "D3", "1" ] }, "SarlByCl": { "opcodes": [ "D3", "7" ] }, "ShllByCl": { "opcodes": [ "D3", "4" ] }, "ShrlByCl": { "opcodes": [ "D3", "5" ] } }, "args": [ { "class": "GeneralReg32/Mem32", "usage": "use_def" }, { "class": "CL", "usage": "use" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "RolwByCl": { "opcodes": [ "66", "D3", "0" ] }, "RorwByCl": { "opcodes": [ "66", "D3", "1" ] }, "SarwByCl": { "opcodes": [ "66", "D3", "7" ] }, "ShlwByCl": { "opcodes": [ "66", "D3", "4" ] }, "ShrwByCl": { "opcodes": [ "66", "D3", "5" ] } }, "args": [ { "class": "GeneralReg16/Mem16", "usage": "use_def" }, { "class": "CL", "usage": "use" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "Rorxl": { "feature": "BMI2", "opcodes": [ "C4", "03", "03", "F0" ] } }, "args": [ { "class": "GeneralReg32", "usage": "def" }, { "class": "GeneralReg32/Mem32", "usage": "use" }, { "class": "Imm8" } ] }, { "encodings": { "Roundsd": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "3A", "0B" ] } }, "args": [ { "class": "FpReg64", "usage": "def" }, { "class": "FpReg64/VecMem64", "usage": "use" }, { "class": "Imm8" } ] }, { "encodings": { "Roundss": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "3A", "0A" ] } }, "args": [ { "class": "FpReg32", "usage": "def" }, { "class": "FpReg32/VecMem32", "usage": "use" }, { "class": "Imm8" } ] }, { "encodings": { "Sahf": { "opcode": "9E" } }, "args": [ { "class": "EAX", "usage": "use" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "Sarxl": { "feature": "BMI2", "opcodes": [ "C4", "02", "02", "F7" ] }, "Shlxl": { "feature": "BMI2", "opcodes": [ "C4", "02", "01", "F7" ] }, "Shrxl": { "feature": "BMI2", "opcodes": [ "C4", "02", "03", "F7" ] } }, "args": [ { "class": "GeneralReg32", "usage": "use_def" }, { "class": "GeneralReg32/Mem32", "usage": "use" }, { "class": "GeneralReg32", "usage": "use" } ] }, { "encodings": { "Setcc": { "opcodes": [ "0F", "90", "0" ] } }, "args": [ { "class": "Cond" }, { "class": "GeneralReg8/Mem8", "usage": "def" }, { "class": "FLAGS", "usage": "use" } ] }, { "encodings": { "Shldl": { "opcodes": [ "0F", "A4" ], "type": "reg_to_rm" }, "Shrdl": { "opcodes": [ "0F", "AC" ], "type": "reg_to_rm" } }, "args": [ { "class": "GeneralReg32/Mem32", "usage": "use_def" }, { "class": "GeneralReg32", "usage": "use" }, { "class": "Imm8" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "ShldlByCl": { "opcodes": [ "0F", "A5" ], "type": "reg_to_rm" }, "ShrdlByCl": { "opcodes": [ "0F", "AD" ], "type": "reg_to_rm" } }, "args": [ { "class": "GeneralReg32/Mem32", "usage": "use_def" }, { "class": "GeneralReg32", "usage": "use" }, { "class": "CL", "usage": "use" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "Shufpd": { "opcodes": [ "66", "0F", "C6" ] }, "Shufps": { "opcodes": [ "0F", "C6" ] } }, "args": [ { "class": "VecReg128", "usage": "use_def" }, { "class": "VecReg128/VecMem128", "usage": "use" }, { "class": "Imm8" } ] }, { "encodings": { "Sqrtsd": { "opcodes": [ "F2", "0F", "51" ] } }, "args": [ { "class": "FpReg64", "usage": "def" }, { "class": "FpReg64/VecMem64", "usage": "use" } ] }, { "encodings": { "Sqrtss": { "opcodes": [ "F3", "0F", "51" ] } }, "args": [ { "class": "FpReg32", "usage": "def" }, { "class": "FpReg32/VecMem32", "usage": "use" } ] }, { "encodings": { "Stmxcsr": { "opcodes": [ "0F", "AE", "3" ] }, "Vstmxcsr": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "AE", "3" ] } }, "args": [ { "class": "Mem32", "usage": "def" } ] }, { "encodings": { "Ucomisd": { "opcodes": [ "66", "0F", "2E" ] } }, "args": [ { "class": "FpReg64", "usage": "use" }, { "class": "FpReg64/VecMem64", "usage": "use" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "Ucomiss": { "opcodes": [ "0F", "2E" ] } }, "args": [ { "class": "FpReg32", "usage": "use" }, { "class": "FpReg32/VecMem32", "usage": "use" }, { "class": "FLAGS", "usage": "def" } ] }, { "encodings": { "Vaddpd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "58" ], "type": "optimizable_using_commutation" }, "Vaddps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "58" ], "type": "optimizable_using_commutation" }, "Vandpd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "54" ], "type": "optimizable_using_commutation" }, "Vandps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "54" ], "type": "optimizable_using_commutation" }, "Vcmpeqpd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "C2", "00" ], "type": "optimizable_using_commutation" }, "Vcmpeqps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "C2", "00" ], "type": "optimizable_using_commutation" }, "Vcmplepd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "C2", "02" ], "type": "vex_rm_to_reg" }, "Vcmpleps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "C2", "02" ], "type": "vex_rm_to_reg" }, "Vcmpltpd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "C2", "01" ], "type": "vex_rm_to_reg" }, "Vcmpltps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "C2", "01" ], "type": "vex_rm_to_reg" }, "Vcmpneqpd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "C2", "04" ], "type": "optimizable_using_commutation" }, "Vcmpneqps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "C2", "04" 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