/*
 * Copyright (c) 2023, MediaTek Inc. All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

/****************************************************************
 * Auto generated by DE, please DO NOT modify this file directly.
 *****************************************************************/

#ifndef MT_SPM_PMIC_WRAP_H
#define MT_SPM_PMIC_WRAP_H

enum pmic_wrap_phase_id {
	PMIC_WRAP_PHASE_ALLINONE = 0,
	NR_PMIC_WRAP_PHASE,
};

/* IDX mapping */
enum {
	CMD_0 = 0,	/* PMIC_WRAP_PHASE_ALLINONE */
	CMD_1,
	CMD_2,
	CMD_3,
	CMD_4,
	CMD_5,
	CMD_6,
	CMD_7,
	CMD_8,
	CMD_9,
	CMD_10,
	CMD_11,
	CMD_12,
	CMD_13,
	CMD_14,
	CMD_15,
	NR_IDX_ALL,
};

/* APIs */
void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase);
void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase, unsigned int idx,
			      unsigned int cmd_wdata);
uint64_t mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase, unsigned int idx);
void mt_spm_dump_pmic_warp_reg(void);

#endif /* MT_SPM_PMIC_WRAP_H */