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| Name | Last modified | Size | Description |
|---|---|---|---|---|
| Parent Directory | - | ||
| AsmParser/ | 2024-12-02 00:54 | - | |
| CMakeLists.txt | 2024-12-02 00:54 | 2.0K | |
| Disassembler/ | 2024-12-02 00:54 | - | |
| GISel/ | 2024-12-02 00:54 | - | |
| MCA/ | 2024-12-02 00:54 | - | |
| MCTargetDesc/ | 2024-12-02 00:54 | - | |
| RISCV.h | 2024-12-02 00:54 | 2.8K | |
| RISCV.td | 2024-12-02 00:54 | 2.3K | |
| RISCVAsmPrinter.cpp | 2024-12-02 00:54 | 17K | |
| RISCVCallingConv.td | 2024-12-02 00:54 | 2.3K | |
| RISCVCodeGenPrepare.cpp | 2024-12-02 00:54 | 5.5K | |
| RISCVExpandAtomicPseudoInsts.cpp | 2024-12-02 00:54 | 24K | |
| RISCVExpandPseudoInsts.cpp | 2024-12-02 00:54 | 14K | |
| RISCVFeatures.td | 2024-12-02 00:54 | 26K | |
| RISCVFrameLowering.cpp | 2024-12-02 00:54 | 52K | |
| RISCVFrameLowering.h | 2024-12-02 00:54 | 3.8K | |
| RISCVGatherScatterLowering.cpp | 2024-12-02 00:54 | 18K | |
| RISCVISelDAGToDAG.cpp | 2024-12-02 00:54 | 108K | |
| RISCVISelDAGToDAG.h | 2024-12-02 00:54 | 6.9K | |
| RISCVISelLowering.cpp | 2024-12-02 00:54 | 555K | |
| RISCVISelLowering.h | 2024-12-02 00:54 | 32K | |
| RISCVInsertVSETVLI.cpp | 2024-12-02 00:54 | 48K | |
| RISCVInstrFormats.td | 2024-12-02 00:54 | 18K | |
| RISCVInstrFormatsC.td | 2024-12-02 00:54 | 5.0K | |
| RISCVInstrFormatsV.td | 2024-12-02 00:54 | 8.4K | |
| RISCVInstrInfo.cpp | 2024-12-02 00:54 | 99K | |
| RISCVInstrInfo.h | 2024-12-02 00:54 | 11K | |
| RISCVInstrInfo.td | 2024-12-02 00:54 | 74K | |
| RISCVInstrInfoA.td | 2024-12-02 00:54 | 17K | |
| RISCVInstrInfoC.td | 2024-12-02 00:54 | 35K | |
| RISCVInstrInfoD.td | 2024-12-02 00:54 | 18K | |
| RISCVInstrInfoF.td | 2024-12-02 00:54 | 28K | |
| RISCVInstrInfoM.td | 2024-12-02 00:54 | 5.2K | |
| RISCVInstrInfoV.td | 2024-12-02 00:54 | 76K | |
| RISCVInstrInfoVPseudos.td | 2024-12-02 00:54 | 263K | |
| RISCVInstrInfoVSDPatterns.td | 2024-12-02 00:54 | 52K | |
| RISCVInstrInfoVVLPatterns.td | 2024-12-02 00:54 | 115K | |
| RISCVInstrInfoXTHead.td | 2024-12-02 00:54 | 6.4K | |
| RISCVInstrInfoXVentana.td | 2024-12-02 00:54 | 5.6K | |
| RISCVInstrInfoZb.td | 2024-12-02 00:54 | 34K | |
| RISCVInstrInfoZfh.td | 2024-12-02 00:54 | 20K | |
| RISCVInstrInfoZicbo.td | 2024-12-02 00:54 | 2.9K | |
| RISCVInstrInfoZk.td | 2024-12-02 00:54 | 7.8K | |
| RISCVMCInstLower.cpp | 2024-12-02 00:54 | 8.2K | |
| RISCVMachineFunctionInfo.cpp | 2024-12-02 00:54 | 1.6K | |
| RISCVMachineFunctionInfo.h | 2024-12-02 00:54 | 5.0K | |
| RISCVMacroFusion.cpp | 2024-12-02 00:54 | 2.4K | |
| RISCVMacroFusion.h | 2024-12-02 00:54 | 1.0K | |
| RISCVMakeCompressible.cpp | 2024-12-02 00:54 | 15K | |
| RISCVMergeBaseOffset.cpp | 2024-12-02 00:54 | 16K | |
| RISCVProcessors.td | 2024-12-02 00:54 | 7.3K | |
| RISCVRedundantCopyElimination.cpp | 2024-12-02 00:54 | 5.7K | |
| RISCVRegisterInfo.cpp | 2024-12-02 00:54 | 29K | |
| RISCVRegisterInfo.h | 2024-12-02 00:54 | 4.0K | |
| RISCVRegisterInfo.td | 2024-12-02 00:54 | 22K | |
| RISCVSExtWRemoval.cpp | 2024-12-02 00:54 | 12K | |
| RISCVSchedRocket.td | 2024-12-02 00:54 | 8.5K | |
| RISCVSchedSiFive7.td | 2024-12-02 00:54 | 8.3K | |
| RISCVSchedSyntacoreSCR1.td | 2024-12-02 00:54 | 6.9K | |
| RISCVSchedule.td | 2024-12-02 00:54 | 11K | |
| RISCVScheduleV.td | 2024-12-02 00:54 | 37K | |
| RISCVScheduleZb.td | 2024-12-02 00:54 | 4.4K | |
| RISCVStripWSuffix.cpp | 2024-12-02 00:54 | 2.6K | |
| RISCVSubtarget.cpp | 2024-12-02 00:54 | 6.5K | |
| RISCVSubtarget.h | 2024-12-02 00:54 | 7.0K | |
| RISCVSystemOperands.td | 2024-12-02 00:54 | 13K | |
| RISCVTargetMachine.cpp | 2024-12-02 00:54 | 13K | |
| RISCVTargetMachine.h | 2024-12-02 00:54 | 2.5K | |
| RISCVTargetObjectFile.cpp | 2024-12-02 00:54 | 4.2K | |
| RISCVTargetObjectFile.h | 2024-12-02 00:54 | 1.7K | |
| RISCVTargetTransformInfo.cpp | 2024-12-02 00:54 | 56K | |
| RISCVTargetTransformInfo.h | 2024-12-02 00:54 | 14K | |
| TargetInfo/ | 2024-12-02 00:54 | - | |