{NAME}{DST_FULL}{SAT}{COND}{SKPHP}{TYPE}{PMODE}{THREAD}{RMODE}
{NAME}
{NAME}{COND}{TYPE}
{NAME}{COND}{SKPHP}{DENORM}{LOCAL}{TYPE}{LEFT_SHIFT}{PMODE}
{DST_USE} == 0
void
t{REG}{AMODE}{COMPS}
{TYPE_BIT2} << 2 | {TYPE_BIT01}
.{SWIZ_X}{SWIZ_Y}{SWIZ_Z}{SWIZ_W}
00000
0000
000
{HIGH_HALF} << 1 | {LOW_HALF}
{SRC_NEG}{SRC_ABS}{SRC_RGROUP}{SRC_REG}{SRC_AMODE}{SRC_SWIZ}{SRC_ABS}
({SRC_AMODE} >> 1)
(({SRC_RGROUP} == 7) & ({IMMED_TYPE} == 0))
{IMMED}
(((({SRC_AMODE} & 0x1) << 19) |
({SRC_ABS} << 18) |
({SRC_NEG} << 17) |
({SRC_SWIZ} << 9) |
{SRC_REG}) << 12)
(({SRC_RGROUP} == 7) & ({IMMED_TYPE} == 1))
{IMMED}
((({SRC_AMODE} & 0x1) << 19) |
({SRC_ABS} << 18) |
({SRC_NEG} << 17) |
({SRC_SWIZ} << 9) |
{SRC_REG})
(({SRC_RGROUP} == 7) & ({IMMED_TYPE} == 2))
{IMMED}
((({SRC_AMODE} & 0x1) << 19) |
({SRC_ABS} << 18) |
({SRC_NEG} << 17) |
({SRC_SWIZ} << 9) |
{SRC_REG})
(({SRC_RGROUP} == 7) & ({IMMED_TYPE} == 3))
{IMMED}
((({SRC_AMODE} & 0x1) << 19) |
({SRC_ABS} << 18) |
({SRC_NEG} << 17) |
({SRC_SWIZ} << 9) |
{SRC_REG})
{NAME} {DST:align=18}{DST_FULL}, void, void, void
0
000000000
00000000
0
0
000
000
0
000000000
00000000
0
0
000
000
0
000000000
00000000
0
0
000
000
({SRC0_USE} != 0) && ({SRC1_USE} != 0)
Needed for texkill
{NAME}{COND}{TYPE}{PMODE}{THREAD}{RMODE} {DST:align=18}{DST_FULL}, void, void, void
{NAME}{COND}{TYPE}{PMODE}{THREAD}{RMODE} {DST:align=18}, {SRC0}, {SRC1}, void
{NAME}{COND}{TYPE}{PMODE}{THREAD}{RMODE} {DST:align=18}, {SRC0}, void, void
0
000000000
00000000
0
0
000
000
{INSTR_ALU} {DST:align=18}, {SRC0}, void, void
1
0
000000000
00000000
0
0
000
000
0
000000000
00000000
0
0
000
000
{INSTR_ALU} {DST:align=18}, void, void, {SRC2}
0
000000000
00000000
0
0
000
000
0
000000000
00000000
0
0
000
000
1
{INSTR_ALU} {DST:align=18}, {SRC0}, {SRC1}, void
1
1
0
000000000
00000000
0
0
000
000
{INSTR_ALU} {DST:align=18}, {SRC0}, void, {SRC2}
1
0
000000000
00000000
0
0
000
000
1
{INSTR_ALU} {DST:align=18}, void, {SRC1}, {SRC2}
0
000000000
00000000
0
0
000
000
1
1
{INSTR_ALU} {DST:align=18}, {SRC0}, {SRC1}, {SRC2}
1
1
1
0
0
0
{INSTR_TEX} {DST:align=18}, tex{TEX_ID}{TEX_SWIZ}, {SRC0}, void, void
1
0
000000000
00000000
0
0
000
000
0
000000000
00000000
0
0
000
000
{INSTR_TEX} {DST:align=18}, tex{TEX_ID}{TEX_SWIZ}, {SRC0}, {SRC1}, {SRC2}
1
1
1
{INSTR_TEX} {DST:align=18}, tex{TEX_ID}{TEX_SWIZ}, {SRC0}, {SRC1}, void
{INSTR_TEX} {DST:align=18}, tex{TEX_ID}{TEX_SWIZ}, {SRC0}, void, void
0
000000000
00000000
0
0
000
000
00000000000000000000
00
x
00000000
0000
0000000000
{INSTR_CF} {:align=18}void, void, void, {TARGET}
0000000000
0000000000
000
0000000000000
0000000000000
000
({SRC0_USE} != 0) && ({SRC1_USE} == 0)
{INSTR_CF} {:align=18}void, {SRC0}, void, {TARGET}
1
0
000000000
00000000
0
0
000
000
{INSTR_CF} {:align=18}void, {SRC0}, {SRC1}, {TARGET}
1
1
{LEFT_SHIFT} != 0
.ls{LEFT_SHIFT}
00000
00
0
0
{HIGH_HALF} << 1 | {LOW_HALF}
{INSTR_LOAD_STORE} {DST:align=18}, {SRC0}, {SRC1}, void
1
1
0
000000000
00000000
0
0
000
000
xxxxx
x
xxxxx
xxxxx
xx
0
x
{HIGH_HALF} << 1 | {LOW_HALF}
{INSTR_LOAD_STORE} {:align=18}mem{COMPS}, {SRC0}, {SRC1}, {SRC2}
1
1
1
000000
0
000001
0
000010
0
000011
0
000101
0
000110
0
000111
0
001000
0
001001
0
001010
0
001100
0
001101
0
001111
0
010000
0
010001
0
010010
0
010011
0
010100
0
010101
0
010110
0
010110
0
010110
0
010111
0
011000
0
011001
0
011010
0
011011
0
100001
0
100010
0
100011
0
100100
0
100101
0
100110
0
100111
0
101010
0
101100
0
101101
0
101110
0
101111
0
110001
0
110010
0
110011
0
111011
0
111100
0
000000
1
000100
1
001000
1
001100
1
001110
1
010110
1
010111
1
011000
1
011001
1
011010
1
011011
1
011100
1
011101
1
011110
1
011111
1
100000
1
100001
1
100100
1
100101
1
100110
1
100111
1
101000
1
101001
1
101010
1
101011
1
101100
1
101101
1
101111
1
110010
1
110011
1
110100
1
110101
1
110110
1
111111
1
{INSTR_ALU} {DST:align=18}, {SRC0}, void, void
1
0
000000000
00000000
0
0
000
000
1
00000000
0
0
100
111
000001011
000001100