Index of /aosp/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU

[ICO]NameLast modifiedSizeDescription

[PARENTDIR]Parent Directory  -  
[DIR]AsmParser/2024-12-02 00:51 -  
[DIR]Disassembler/2024-12-02 00:51 -  
[DIR]MCTargetDesc/2024-12-02 00:51 -  
[DIR]TargetInfo/2024-12-02 00:51 -  
[DIR]Utils/2024-12-02 00:51 -  
[TXT]R600MachineFunctionInfo.cpp2024-12-02 00:51 551  
[   ]VIInstrFormats.td2024-12-02 00:51 645  
[   ]AMDGPURegisterInfo.td2024-12-02 00:51 666  
[TXT]AMDGPUMacroFusion.h2024-12-02 00:51 679  
[   ]VIInstructions.td2024-12-02 00:51 683  
[   ]R700Instructions.td2024-12-02 00:51 783  
[   ]AMDGPURegisterBanks.td2024-12-02 00:51 798  
[TXT]AMDGPUGlobalISelUtils.h2024-12-02 00:51 813  
[TXT]R600MachineFunctionInfo.h2024-12-02 00:51 824  
[TXT]LLVMBuild.txt2024-12-02 00:51 1.1K 
[TXT]AMDGPURegisterInfo.h2024-12-02 00:51 1.1K 
[TXT]AMDGPUTargetObjectFile.h2024-12-02 00:51 1.2K 
[TXT]R600FrameLowering.h2024-12-02 00:51 1.3K 
[TXT]AMDGPUPTNote.h2024-12-02 00:51 1.3K 
[TXT]AMDGPUMachineModuleInfo.cpp2024-12-02 00:51 1.3K 
[TXT]AMDGPUFrameLowering.h2024-12-02 00:51 1.4K 
[TXT]AMDGPUInstrInfo.h2024-12-02 00:51 1.5K 
[TXT]R600AsmPrinter.h2024-12-02 00:51 1.5K 
[   ]R600.td2024-12-02 00:51 1.5K 
[TXT]AMDGPUGlobalISelUtils.cpp2024-12-02 00:51 1.5K 
[TXT]AMDGPUTargetObjectFile.cpp2024-12-02 00:51 1.5K 
[   ]R600Schedule.td2024-12-02 00:51 1.6K 
[TXT]AMDGPUPerfHintAnalysis.h2024-12-02 00:51 1.7K 
[TXT]AMDGPUInstrInfo.cpp2024-12-02 00:51 1.7K 
[TXT]R600RegisterInfo.h2024-12-02 00:51 1.8K 
[TXT]AMDGPUFixFunctionBitcasts.cpp2024-12-02 00:51 1.8K 
[TXT]R600FrameLowering.cpp2024-12-02 00:51 1.9K 
[TXT]AMDGPUFrameLowering.cpp2024-12-02 00:51 2.0K 
[TXT]SIFixVGPRCopies.cpp2024-12-02 00:51 2.0K 
[TXT]SIProgramInfo.h2024-12-02 00:51 2.0K 
[TXT]AMDGPUMachineFunction.h2024-12-02 00:51 2.1K 
[   ]AMDGPUFeatures.td2024-12-02 00:51 2.1K 
[TXT]AMDGPUMacroFusion.cpp2024-12-02 00:51 2.2K 
[TXT]AMDGPUCallLowering.h2024-12-02 00:51 2.3K 
[TXT]AMDGPUMachineFunction.cpp2024-12-02 00:51 2.4K 
[TXT]R600MachineScheduler.h2024-12-02 00:51 2.5K 
[TXT]SIFrameLowering.h2024-12-02 00:51 3.2K 
[TXT]AMDGPUAliasAnalysis.h2024-12-02 00:51 3.4K 
[TXT]GCNSchedStrategy.h2024-12-02 00:51 3.5K 
[TXT]R600RegisterInfo.cpp2024-12-02 00:51 3.7K 
[TXT]GCNIterativeScheduler.h2024-12-02 00:51 3.8K 
[TXT]CMakeLists.txt2024-12-02 00:51 3.9K 
[TXT]GCNHazardRecognizer.h2024-12-02 00:51 4.0K 
[TXT]R600Defines.h2024-12-02 00:51 4.2K 
[TXT]AMDGPULowerIntrinsics.cpp2024-12-02 00:51 4.3K 
[   ]R600Processors.td2024-12-02 00:51 4.4K 
[TXT]AMDGPUTargetMachine.h2024-12-02 00:51 4.4K 
[TXT]AMDGPUUnifyMetadata.cpp2024-12-02 00:51 4.5K 
[TXT]R600AsmPrinter.cpp2024-12-02 00:51 4.5K 
[TXT]AMDGPUAlwaysInlinePass.cpp2024-12-02 00:51 4.5K 
[TXT]AMDGPUArgumentUsageInfo.h2024-12-02 00:51 4.7K 
[   ]GCNProcessors.td2024-12-02 00:51 4.8K 
[TXT]R600ISelLowering.h2024-12-02 00:51 4.8K 
[TXT]AMDGPULegalizerInfo.h2024-12-02 00:51 5.1K 
[TXT]AMDGPUAsmPrinter.h2024-12-02 00:51 5.1K 
[TXT]AMDGPUOpenCLEnqueuedBlockLowering.cpp2024-12-02 00:51 5.3K 
[TXT]AMDGPUArgumentUsageInfo.cpp2024-12-02 00:51 5.3K 
[TXT]AMDGPUAliasAnalysis.cpp2024-12-02 00:51 5.4K 
[TXT]AMDGPUMachineModuleInfo.h2024-12-02 00:51 5.5K 
[TXT]AMDGPUHSAMetadataStreamer.h2024-12-02 00:51 5.5K 
[TXT]AMDGPUAnnotateUniformValues.cpp2024-12-02 00:51 6.0K 
[TXT]SIPreAllocateWWMRegs.cpp2024-12-02 00:51 6.1K 
[TXT]SIAddIMGInit.cpp2024-12-02 00:51 6.4K 
[TXT]AMDGPURegisterInfo.cpp2024-12-02 00:51 6.5K 
[TXT]AMDGPURegisterBankInfo.h2024-12-02 00:51 6.6K 
[   ]AMDGPUCallingConv.td2024-12-02 00:51 6.7K 
[   ]SISchedule.td2024-12-02 00:51 6.9K 
[   ]AMDGPUGISel.td2024-12-02 00:51 7.3K 
[TXT]R600ClauseMergePass.cpp2024-12-02 00:51 7.4K 
[TXT]AMDGPUInstructionSelector.h2024-12-02 00:51 7.4K 
[TXT]AMDGPULowerKernelAttributes.cpp2024-12-02 00:51 7.8K 
[   ]CaymanInstructions.td2024-12-02 00:51 7.9K 
[TXT]AMDGPUInline.cpp2024-12-02 00:51 8.0K 
[TXT]GCNMinRegStrategy.cpp2024-12-02 00:51 8.2K 
[TXT]AMDGPULowerKernelArguments.cpp2024-12-02 00:51 8.4K 
[   ]AMDGPUGenRegisterBankInfo.def2024-12-02 00:51 8.5K 
[TXT]SIFixupVectorISel.cpp2024-12-02 00:51 8.6K 
[TXT]GCNRegPressure.h2024-12-02 00:51 8.8K 
[   ]SIInstrFormats.td2024-12-02 00:51 9.4K 
[   ]R600RegisterInfo.td2024-12-02 00:51 9.7K 
[TXT]AMDGPUPropagateAttributes.cpp2024-12-02 00:51 9.9K 
[TXT]R600ExpandSpecialInstrs.cpp2024-12-02 00:51 10K 
[TXT]AMDGPUTargetTransformInfo.h2024-12-02 00:51 10K 
[TXT]AMDGPU.h2024-12-02 00:51 11K 
[TXT]GCNNSAReassign.cpp2024-12-02 00:51 11K 
[TXT]AMDGPULibFunc.h2024-12-02 00:51 11K 
[TXT]AMDGPUAnnotateKernelFeatures.cpp2024-12-02 00:51 11K 
[TXT]SIAnnotateControlFlow.cpp2024-12-02 00:51 11K 
[TXT]SILowerSGPRSpills.cpp2024-12-02 00:51 11K 
[TXT]GCNILPSched.cpp2024-12-02 00:51 11K 
[   ]R600InstrFormats.td2024-12-02 00:51 12K 
[TXT]SIRegisterInfo.h2024-12-02 00:51 12K 
[TXT]R600OpenCLImageTypeLoweringPass.cpp2024-12-02 00:51 12K 
[TXT]R600EmitClauseMarkers.cpp2024-12-02 00:51 12K 
[TXT]AMDGPUPerfHintAnalysis.cpp2024-12-02 00:51 12K 
[TXT]SIFormMemoryClauses.cpp2024-12-02 00:51 13K 
[TXT]AMDGPUUnifyDivergentExitNodes.cpp2024-12-02 00:51 13K 
[TXT]SIOptimizeExecMasking.cpp2024-12-02 00:51 13K 
[TXT]R600OptimizeVectorRegisters.cpp2024-12-02 00:51 13K 
[TXT]R600Packetizer.cpp2024-12-02 00:51 13K 
[TXT]R600MachineScheduler.cpp2024-12-02 00:51 14K 
[TXT]R600InstrInfo.h2024-12-02 00:51 14K 
[TXT]AMDGPUMCInstLower.cpp2024-12-02 00:51 14K 
[TXT]SIOptimizeExecMaskingPreRA.cpp2024-12-02 00:51 15K 
[TXT]SIMachineScheduler.h2024-12-02 00:51 16K 
[TXT]SIInsertSkips.cpp2024-12-02 00:51 16K 
[TXT]AMDGPURewriteOutArguments.cpp2024-12-02 00:51 16K 
[TXT]SIModeRegister.cpp2024-12-02 00:51 16K 
[TXT]GCNRegPressure.cpp2024-12-02 00:51 16K 
[TXT]SIMachineFunctionInfo.cpp2024-12-02 00:51 17K 
[   ]AMDGPUInstrInfo.td2024-12-02 00:51 17K 
[TXT]SILowerControlFlow.cpp2024-12-02 00:51 18K 
[TXT]AMDGPUISelLowering.h2024-12-02 00:51 19K 
[TXT]GCNDPPCombine.cpp2024-12-02 00:51 19K 
[TXT]SIDefines.h2024-12-02 00:51 20K 
[TXT]SIISelLowering.h2024-12-02 00:51 20K 
[TXT]GCNIterativeScheduler.cpp2024-12-02 00:51 20K 
[   ]AMDGPUSearchableTables.td2024-12-02 00:51 20K 
[TXT]GCNSchedStrategy.cpp2024-12-02 00:51 21K 
[TXT]AMDGPUPrintfRuntimeBinding.cpp2024-12-02 00:51 22K 
[TXT]R600ControlFlowFinalizer.cpp2024-12-02 00:51 23K 
[   ]VOPInstructions.td2024-12-02 00:51 24K 
[TXT]AMDGPUAtomicOptimizer.cpp2024-12-02 00:51 24K 
[   ]AMDGPUInstructions.td2024-12-02 00:51 25K 
[TXT]AMDGPUCallLowering.cpp2024-12-02 00:51 25K 
[TXT]GCNRegBankReassign.cpp2024-12-02 00:51 26K 
[TXT]SIMachineFunctionInfo.h2024-12-02 00:51 26K 
[   ]VOP3PInstructions.td2024-12-02 00:51 27K 
[TXT]SIShrinkInstructions.cpp2024-12-02 00:51 27K 
[TXT]SILowerI1Copies.cpp2024-12-02 00:51 28K 
[   ]EvergreenInstructions.td2024-12-02 00:51 28K 
[TXT]SIFixSGPRCopies.cpp2024-12-02 00:51 28K 
[TXT]AMDGPUPromoteAlloca.cpp2024-12-02 00:51 30K 
[TXT]SIWholeQuadMode.cpp2024-12-02 00:51 31K 
[   ]SIRegisterInfo.td2024-12-02 00:51 31K 
[TXT]AMDGPUSubtarget.cpp2024-12-02 00:51 31K 
[TXT]AMDKernelCodeT.h2024-12-02 00:51 33K 
[TXT]AMDGPUHSAMetadataStreamer.cpp2024-12-02 00:51 33K 
[TXT]AMDGPUTargetTransformInfo.cpp2024-12-02 00:51 33K 
[TXT]AMDGPUCodeGenPrepare.cpp2024-12-02 00:51 34K 
[   ]AMDGPU.td2024-12-02 00:51 34K 
[   ]VOP1Instructions.td2024-12-02 00:51 36K 
[TXT]AMDGPUSubtarget.h2024-12-02 00:51 36K 
[   ]MIMGInstructions.td2024-12-02 00:51 36K 
[TXT]AMDGPULibFunc.cpp2024-12-02 00:51 38K 
[TXT]AMDGPUTargetMachine.cpp2024-12-02 00:51 40K 
[TXT]SIInstrInfo.h2024-12-02 00:51 41K 
[TXT]SIFrameLowering.cpp2024-12-02 00:51 42K 
[TXT]SIPeepholeSDWA.cpp2024-12-02 00:51 43K 
[TXT]SIMemoryLegalizer.cpp2024-12-02 00:51 45K 
[TXT]GCNHazardRecognizer.cpp2024-12-02 00:51 45K 
[   ]SMInstructions.td2024-12-02 00:51 47K 
[TXT]AMDGPUAsmPrinter.cpp2024-12-02 00:51 48K 
[TXT]R600InstrInfo.cpp2024-12-02 00:51 49K 
[   ]VOP3Instructions.td2024-12-02 00:51 50K 
[   ]DSInstructions.td2024-12-02 00:51 52K 
[TXT]SIFoldOperands.cpp2024-12-02 00:51 54K 
[TXT]AMDGPULibCalls.cpp2024-12-02 00:51 55K 
[   ]R600Instructions.td2024-12-02 00:51 55K 
[TXT]AMDILCFGStructurizer.cpp2024-12-02 00:51 56K 
[TXT]SIInsertWaitcnts.cpp2024-12-02 00:51 57K 
[   ]SOPInstructions.td2024-12-02 00:51 58K 
[   ]SIInstructions.td2024-12-02 00:51 61K 
[   ]VOPCInstructions.td2024-12-02 00:51 63K 
[   ]VOP2Instructions.td2024-12-02 00:51 64K 
[   ]FLATInstructions.td2024-12-02 00:51 65K 
[TXT]SIRegisterInfo.cpp2024-12-02 00:51 65K 
[TXT]SIMachineScheduler.cpp2024-12-02 00:51 69K 
[TXT]SILoadStoreOptimizer.cpp2024-12-02 00:51 71K 
[TXT]AMDGPUInstructionSelector.cpp2024-12-02 00:51 79K 
[TXT]R600ISelLowering.cpp2024-12-02 00:51 82K 
[TXT]AMDGPULegalizerInfo.cpp2024-12-02 00:51 83K 
[   ]SIInstrInfo.td2024-12-02 00:51 90K 
[TXT]AMDGPUISelDAGToDAG.cpp2024-12-02 00:51 98K 
[TXT]AMDGPUMachineCFGStructurizer.cpp2024-12-02 00:51 102K 
[   ]BUFInstructions.td2024-12-02 00:51 109K 
[TXT]AMDGPURegisterBankInfo.cpp2024-12-02 00:51 124K 
[TXT]AMDGPUISelLowering.cpp2024-12-02 00:51 168K 
[TXT]SIInstrInfo.cpp2024-12-02 00:51 227K 
[TXT]SIISelLowering.cpp2024-12-02 00:51 399K 

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